Intel 41210 Benutzerhandbuch

27

 lists the transactions that the 41210 supports when the PCI interface is in the PCI-X mode. 

As a master, the 41210 supports the memory write block command for writes that are multiples of 
cache-line.

Any memory read line or memory read multiple commands on PCI that are decoded by the 41210 
are prefetched on the PCI Express* interface. The prefetchability of a given PCI read request is 
determined by the prefetch policy (PP) bits[55:54] of the 

. The amount of data prefetched depends on the clock frequency, 

x_REQ64#, and the command type. The 41210 does not prefetch past a 4 KB page boundary.

Interrupt acknowledge

0000

No

No

Special cycle
(PCI Express* Type1-to-PCI Special Cycle)

0001

Yes

No

I/O read

0010

Yes

Yes

I/O write

0011

Yes

Yes

Reserved

0100

No

No

Reserved

0101

No

No

Memory read DWORD

0110

Yes

Yes

Memory write

0111

Yes

Yes

Alias to memory read block

1000

No

Yes

Alias to memory write block

1001

No

Yes

Configuration read

1010

Yes

Yes

Configuration write

1011

Yes

Yes

Split completion

1100

Yes

Yes

Dual address cycle

1101

Yes

Yes

Memory read block

1110

Yes

Yes

Memory write block

1111

Yes

Yes

LOCK transaction

–

Yes

No

1. PCI command encodings that are not detailed in this table are ignored.
2. Upstream Type 0 configuration cycles to the bridge’s own configuration space are supported.