Intel 41210 Benutzerhandbuch
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Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
PCI-X Interface
3.3
PCI-X Protocol Specifics
3.3.1
Attributes
describes how the 41210 fills in attribute fields where the PCI-to-PCI Bridge
Specification, Revision 1.1 allows some implementation flexibility.
3.3.2
4 GB and 4 K Page Crossover
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, allows burst transactions
to cross page boundaries (in the case of the 41210, this is 4 K) and 4 GB address boundaries. As a
PCI-X master, the 41210 always ends the transaction at a 4 K boundary. As a PCI-X target, the
41210 allows a burst beyond a 4 K page boundary. Note that on PCI Express*, neither read nor
write requests ever cross a 4 K boundary.
to cross page boundaries (in the case of the 41210, this is 4 K) and 4 GB address boundaries. As a
PCI-X master, the 41210 always ends the transaction at a 4 K boundary. As a PCI-X target, the
41210 allows a burst beyond a 4 K page boundary. Note that on PCI Express*, neither read nor
write requests ever cross a 4 K boundary.
3.3.3
Wait States
The 41210 does not generate wait states as a target.
Table 16.
Intel
®
41210 Serial to Parallel PCI Bridge Implementation of Requester Attribute
Fields
Attribute
Function
No Snoop (NS)
The Intel
®
41210 Serial to Parallel PCI Bridge only forwards this attribute in both
directions and does nothing with it internally.
Relaxed Ordering (RO)
This bit allows relaxed ordering of transactions, which the 41210 does not permit.
This bit is only forwarded in the 41210, and is never generated on PCI-X from an
PCI Express* packet or vice-versa.
This bit is only forwarded in the 41210, and is never generated on PCI-X from an
PCI Express* packet or vice-versa.
Tag
Since the 41210 can have two outstanding requests on PCI-X at a time, this field can
be either 0 or 1.
be either 0 or 1.
Byte counts
From PCI Express*, this attribute is based on the length field from PCI Express*,
which is DWord-based.
which is DWord-based.