Intel 41210 Benutzerhandbuch
70
Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
Error Handling
11.2.1
Error Types
PCI errors are classified into two categories: fatal and non-fatal:
•
Fatal errors are those that have the potential to cause data corruption. Software must be careful
to contain and escalate these errors (when needed).
to contain and escalate these errors (when needed).
•
Non-fatal errors are those that do not cause any data corruption. These errors include driver
errors such as master-abort on PCI and target errors such as target-abort.
errors such as master-abort on PCI and target errors such as target-abort.
All errors on PCI are uncorrectable and are forwarded to PCI Express* as such.
The fatal class of errors includes:
•
Data parity errors on PCI
•
Address and attribute parity errors on PCI
The non-fatal class of errors includes:
•
Target Aborts on PCI
•
Master Aborts on PCI
11.2.2
Termination of Completion Required Transactions
11.2.2.1
Immediate Termination on the PCI-X Interface
An immediate termination occurs when the 41210 Bridge masters a transaction on PCI or PCI-X
and receives an “immediate termination” response for that transaction.
and receives an “immediate termination” response for that transaction.
describes the
completion-status translation for immediate terminations. The behavior described for completion-
required cycles is independent of the setting of the Master Abort Mode bit, and is also independent
of whether the cycle is exclusive (locked) or not.
required cycles is independent of the setting of the Master Abort Mode bit, and is also independent
of whether the cycle is exclusive (locked) or not.
Table 29.
Completion-Status Translation for Immediate Terminations
PCI-X Termination
PCI Express* Completion
Normal completion
Successful
Normal completion with
data parity error
data parity error
Memory, I/O, configuration reads
Successful with poisoned TLP
Configuration, I/O writes
UR
Configuration write to special cycle
conversion
conversion
Successful
Master abort
UR
Target abort
CA
NOTES:
1. In PCI mode, the Intel
®
41210 Serial to Parallel PCI Bridge samples PERR# asserted and generates the
UR completion.
2. PERR# is not signaled for a special cycle data parity error. SERR# is asserted instead.