Acer Intel Celeron G530 KC.53001.CDG Benutzerhandbuch
Produktcode
KC.53001.CDG
42
Intel
®
Celeron
®
Processor on 0.13 Micron Process in the 478-Pin Package
Datasheet
System Bus Signal Quality Specifications
3.2
System Bus Signal Quality Specifications and
Measurement Guidelines
Measurement Guidelines
Various scenarios have been simulated to generate a set of AGTL+ layout guidelines that are
available in the Platform Design Guideline.
available in the Platform Design Guideline.
provides the signal quality specifications for all processor signals for use in simulating
signal quality at the processor core silicon. The Celeron processor on 0.13 micron process
maximum allowable overshoot and undershoot specifications are provided in
maximum allowable overshoot and undershoot specifications are provided in
through
shows the system bus ringback tolerance for low-to-high transitions, and
shows ringback tolerance for high-to-low transitions.
Figure 21. BCLK Signal Integrity Waveform
Crossing
Voltage
Threshold
Region
VH
VL
Overshoot
Undershoot
Ringback
Margin
Rising Edge
Ringback
Falling Edge
Ringback,
BCLK0
BCLK1
Crossing
Voltage
Table 24. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signals Groups
Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Notes
1,2,3,4,5,6,7
NOTES:
1.
All signal integrity specifications are measured at the processor silicon.
2.
Unless otherwise noted, all specifications in this table apply to all Celeron processor on 0.13 micron process
frequencies.
frequencies.
3.
Specifications are for the edge rate of 0.3 – 4.0 V/ns.
4.
All values specified by design characterization.
5.
See
for maximum allowable overshoot duration.
6.
Ringback between GTLREF + 10% and GTLREF – 10% is not supported.
7.
Intel recommends that simulations not exceed a ringback value of GTLREF ± 200 mV to allow margin for
other sources of system noise.
other sources of system noise.
All Signals
0
→
1
GTLREF + 10%
V
All Signals
1
→
0
GTLREF – 10%
V