Acer Intel Celeron G530 KC.53001.CDG Benutzerhandbuch
Produktcode
KC.53001.CDG
Intel
®
Celeron
®
Processor on 0.13 Micron Process in the 478-Pin Package Datasheet
43
System Bus Signal Quality Specifications
Table 25. Ringback Specifications for PWRGOOD Input and TAP Signal Group
Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Notes
1,2,3,4
NOTES:
1.
All signal integrity specifications are measured at the processor silicon.
2.
Unless otherwise noted, all specifications in this table apply to all Celeron processor on 0.13 micron process
frequencies.
frequencies.
3.
See
for maximum allowable overshoot.
4.
See
for the DC specifications.
TAP and PWRGOOD
0
→
1
V
t+(max)
TO V
t-(max)
V
TAP and PWRGOOD
1
→
0
V
t-(min)
TO V
t+(min)
V
Figure 22. Low-to-High System Bus Receiver Ringback Tolerance
GTLREF
V
CC
Noise
Margin
Margin
+10% GTLREF
-10% GTLREF
V
SS
Figure 23. High-to-Low System Bus Receiver Ringback Tolerance
Noise
Margin
Margin
GTLREF
+10% GTLREF
-10% GTLREF
V
CC
V
SS