Intel MFS5000SI MFS5000SIB Benutzerhandbuch
Produktcode
MFS5000SIB
2BFunctional Architecture
Intel® Compute Module MFS5000SI TPS
3.1.2.2
Common Enabling Kit (CEK) Design Support
The compute module complies with Intel’s Common Enabling Kit (CEK) processor mounting and heatsink
retention solution. The compute module ships with a CEK spring snapped onto the underside of the
server board, beneath each processor socket. The heatsink attaches to the CEK, over the top of the
processor and the thermal interface material (TIM). For the stacking order of the chassis, CEK spring,
server board, TIM, and heatsink, see the following figure.
retention solution. The compute module ships with a CEK spring snapped onto the underside of the
server board, beneath each processor socket. The heatsink attaches to the CEK, over the top of the
processor and the thermal interface material (TIM). For the stacking order of the chassis, CEK spring,
server board, TIM, and heatsink, see the following figure.
The CEK spring is removable, allowing for the use of non-Intel heatsink retention solutions.
Note:
The processor heatsink and CEK spring shown in the following diagram are for reference purposes
only. The actual processor heatsink and CEK solutions compatible with this generation server board may
be of a different design.
be of a different design.
Heatsink assembly
Thermal interface material (TIM)
Server board
CEK spring
Chassis
Figure 5. CEK Processor Mounting
3.1.3
Memory Subsystem
The MCH masters four fully buffered DIMM (FBD) memory channels. FBD memory utilizes a narrow high-
speed frame-oriented interface referred to as a channel. The four FBD channels are organized into two
branches of two channels per branch. Each branch is supported by a separate memory controller. The
two channels on each branch operate in lock step to increase FBD bandwidth. On the server board, the
four channels are routed to eight DIMM slots and are capable of supporting registered DDR2-533 and
DDR2-667 FBDIMM memory (stacked or unstacked). Peak theoretical memory data bandwidth is 6.4
GB/s with DDR2-533 and 8.0 GB/s with DDR2-667.
speed frame-oriented interface referred to as a channel. The four FBD channels are organized into two
branches of two channels per branch. Each branch is supported by a separate memory controller. The
two channels on each branch operate in lock step to increase FBD bandwidth. On the server board, the
four channels are routed to eight DIMM slots and are capable of supporting registered DDR2-533 and
DDR2-667 FBDIMM memory (stacked or unstacked). Peak theoretical memory data bandwidth is 6.4
GB/s with DDR2-533 and 8.0 GB/s with DDR2-667.
On the Intel
®
Compute Module MFS5000SI, a pair of channels becomes a branch where Branch 0
consists of channels A and B, and Branch 1 consists of channels C and D. FBD memory channels are
organized into two branches for RAID 1 (mirroring) support.
organized into two branches for RAID 1 (mirroring) support.
Revision 1.4
Intel order number: E15154-007
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