Intel MFS5000SI MFS5000SIB Benutzerhandbuch
Produktcode
MFS5000SIB
Intel® Compute Module MFS5000SI TPS
2BFunctional Architecture
Revision 1.4
9
Intel order number: E15154-007
TP02299
DIMM D2
DIMM D1
DIMM C2
DIMM C1
DIMM B2
DIMM B1
DIMM A2
DIMM A1
Branch 0
MCH
Channel A
Channel B
Channel D
Channel C
Branch 1
Figure 6. Memory Layout
To boot the system, the system BIOS on the server board uses a dedicated I
2
C bus to retrieve DIMM
information needed to program the MCH memory registers. The following table provides the I
2
C
addresses for each DIMM slot.
Table 1. I
2
C Addresses for Memory Module SMB
Device
Address
DIMM A1
0xA0
DIMM A2
0xA2
DIMM B1
0xA0
DIMM B2
0xA2
DIMM C1
0xA0
DIMM C2
0xA2
DIMM D1
0xA0
DIMM D2
0xA2
3.1.3.1
Memory RASUM Features
The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and
Manageability) features. These features include the Intel
Manageability) features. These features include the Intel
®
x4 Single Device Data Correction (Intel
®
x4
SDDC) for memory error detection and correction, Memory Scrubbing, Retry on Correctable Errors,
Memory Built In Self Test, DIMM Sparing, and Memory Mirroring. For more information regarding these
features, see the Intel
Memory Built In Self Test, DIMM Sparing, and Memory Mirroring. For more information regarding these
features, see the Intel
®
5000 Series Chipsets Server Board Family Datasheet
.
1
DIMM Sparing and Memory Mirroring features will be made available post production launch with a BIOS update.