Texas Instruments DAC8728EVM - DAC8728 Evaluation Module DAC8728EVM DAC8728EVM Datenbogen
Produktcode
DAC8728EVM
Digital Interface
www.ti.com
The analog interface is populated on the top and the bottom of the evaluation board. All of the output pins
are routed directly from the DAC8728 to the J5 connector. Additionally, they can be routed through an
OPA277 buffer circuit using JP1 and JP2. The output of the buffer circuit is routed to TP3 and TP4.
are routed directly from the DAC8728 to the J5 connector. Additionally, they can be routed through an
OPA277 buffer circuit using JP1 and JP2. The output of the buffer circuit is routed to TP3 and TP4.
The output of the DAC8728 internal offset DAC is routed to test points TP10 and TP17.
The DAC8728EVM has two external reference voltage options. J2.2 controls the external reference
voltage for the REF-A input. J2.1 controls the reference for the REF-B input. When an external reference
is used, jumpers JP4-JP7 must be configured properly. Test points TP8 and TP7 can be used to verify
that the jumpers are configured properly and the correct reference voltage is applied to the DAC.
voltage for the REF-A input. J2.1 controls the reference for the REF-B input. When an external reference
is used, jumpers JP4-JP7 must be configured properly. Test points TP8 and TP7 can be used to verify
that the jumpers are configured properly and the correct reference voltage is applied to the DAC.
The V
MON
output allows the user to relay any of the DAC outputs, as well as A
IN
-0 or A
IN
-1, to a single pin.
V
MON
is routed to test point TP9 and is connected to a 0.1
m
F capacitor.
3
Digital Interface
The DAC8728EVM is designed for easy interfacing to multiple control platforms. To achieve this host
processor flexibility, an unconventional way of controlling this EVM had to be developed. Therefore, the
16-bit data bus from the host processor is shared between the 16-bit data bus and the 5-bit A0–A4
address bus on the DAC8728. This configuration is accomplished with the use of the SN74LVC374 8-bit
Rising-Edge Triggered Latch (U11 on EVM). As a result, every write or read operation to the DAC8728 is
a two-step process. The first step writes the appropriate A0–A4 address to the first five bits of the data bus
and latches it into the SN74LVC374; this process sets up the appropriate address for the DAC8728. The
second step writes to (or reads from) the selected address data with all 16 bits of the parallel data bus.
processor flexibility, an unconventional way of controlling this EVM had to be developed. Therefore, the
16-bit data bus from the host processor is shared between the 16-bit data bus and the 5-bit A0–A4
address bus on the DAC8728. This configuration is accomplished with the use of the SN74LVC374 8-bit
Rising-Edge Triggered Latch (U11 on EVM). As a result, every write or read operation to the DAC8728 is
a two-step process. The first step writes the appropriate A0–A4 address to the first five bits of the data bus
and latches it into the SN74LVC374; this process sets up the appropriate address for the DAC8728. The
second step writes to (or reads from) the selected address data with all 16 bits of the parallel data bus.
The four address bits from the host processor are used to control the SN74LVC139, a two-channel,
two-to-four line decoder/demultiplexer (U7 on EVM). This device is used to create eight control bits from
the processor address that are used around the board to control various signals such as the LATCH input
to the SN74LVC374 and the DC_CS (daughter card chip select). For every write or read operation, the
appropriate signals must be selected; therefore, specific address combinations are used to achieve
different results. These combinations are explored further in the next section.
two-to-four line decoder/demultiplexer (U7 on EVM). This device is used to create eight control bits from
the processor address that are used around the board to control various signals such as the LATCH input
to the SN74LVC374 and the DC_CS (daughter card chip select). For every write or read operation, the
appropriate signals must be selected; therefore, specific address combinations are used to achieve
different results. These combinations are explored further in the next section.
Jumper options are provided on the board to allow direct hardware control over the digital control pins:
LDAC, CLR, RST, RSTSEL, and USB/BTC. Jumpers JP3, JP9 to JP11, JP13, and JP17 can be set to
allow the outputs of the SN74LVC139 to control the LATCH_CTRL, R/W, CLR, RST, DC_CS, and
LDAC_CTRL signals on the EVM.
LDAC, CLR, RST, RSTSEL, and USB/BTC. Jumpers JP3, JP9 to JP11, JP13, and JP17 can be set to
allow the outputs of the SN74LVC139 to control the LATCH_CTRL, R/W, CLR, RST, DC_CS, and
LDAC_CTRL signals on the EVM.
Onboard digital logic is used to control the DAC8728 CS pin. The WE and RE pins and the DC_CS output
of the SN74LVC139 (U7) are used to derive the appropriate DAC8728 CS signal. JP10 allows the user to
choose between three addresses to control the DC_CS signal on the EVM. Having this ability to select the
address of the DAC8728 enables the possibility of stacking other EVM boards on top of the
DAC8728EVM.
of the SN74LVC139 (U7) are used to derive the appropriate DAC8728 CS signal. JP10 allows the user to
choose between three addresses to control the DC_CS signal on the EVM. Having this ability to select the
address of the DAC8728 enables the possibility of stacking other EVM boards on top of the
DAC8728EVM.
Jumpers JP17, JP9, and JP3 control the LDAC, RST, and CLR pins, respectively. The default state of all
these jumpers is a shunt across pins 1 and 2 of the header. This shunt routes the software-controlled
outputs from the SN74LVC139 (U7) to the DAC8728. By removing the shunts on these jumpers, the
default hardware state for these pins is selected: high for CLR and RST, and low for LDAC. By shunting
pins 2 and 3 of these headers, the opposite hardware states for these pins are selected. Alternatively, with
the jumpers removed, the user can apply external signals to pin 2 of these jumpers to control the signals
via an external source.
these jumpers is a shunt across pins 1 and 2 of the header. This shunt routes the software-controlled
outputs from the SN74LVC139 (U7) to the DAC8728. By removing the shunts on these jumpers, the
default hardware state for these pins is selected: high for CLR and RST, and low for LDAC. By shunting
pins 2 and 3 of these headers, the opposite hardware states for these pins are selected. Alternatively, with
the jumpers removed, the user can apply external signals to pin 2 of these jumpers to control the signals
via an external source.
Jumper JP11 and JP13 control the USB/BTC and RSTSEL pins on the DAC8728. Applying a shunt across
these jumpers ties the respective pin to GND. By removing the shunt, the pin is connected to IOV
these jumpers ties the respective pin to GND. By removing the shunt, the pin is connected to IOV
DD
through a pull-up resistor.
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DAC8728EVM
SBAU161 – February 2010
Copyright © 2010, Texas Instruments Incorporated