Texas Instruments LM96080 Evaluation Board LM96080EB/NOPB LM96080EB/NOPB Datenbogen
Produktcode
LM96080EB/NOPB
SNAS465D – SEPTEMBER 2009 – REVISED MARCH 2013
When using a single byte read, the 8 MSbs of the Temperature reading can be found at Value RAM (address
27h). The remainder of the Temperature reading can be found in the OS Configuration/Temperature Resolution
Register (address 06h), bits 4-7. In 9-bit format, bit 7 is the only valid bit. In addition, all 9 or 12 bits can be read
using a double byte read at register address 27h.
27h). The remainder of the Temperature reading can be found in the OS Configuration/Temperature Resolution
Register (address 06h), bits 4-7. In 9-bit format, bit 7 is the only valid bit. In addition, all 9 or 12 bits can be read
using a double byte read at register address 27h.
Temperature Interrupts
There are four Value RAM WATCHDOG limits for the Temperature reading that affect the INT and OS outputs of
the LM96080. They are: T
the LM96080. They are: T
hot
, T
hot hyst
, T
os
, and T
os hyst
Limit Registers (addresses 38h - 3Bh). There are three
interrupt modes of operation: “Default Interrupt” mode, “One-Time Interrupt” mode, and “Comparator Mode”. The
OS output of the LM96080 can be programmed for “One-Time Interrupt” mode and “Comparator” mode. INT can
be programmed for “Default Interrupt” mode and “One-Time” Interrupt. These modes are explained below and
shown in
OS output of the LM96080 can be programmed for “One-Time Interrupt” mode and “Comparator” mode. INT can
be programmed for “Default Interrupt” mode and “One-Time” Interrupt. These modes are explained below and
shown in
“Default Interrupt mode” operates in the following way: Exceeding T
hot
causes an Interrupt that will remain
active indefinitely until reset by reading Interrupt Status Register 1 (address 01h) or cleared by the INT_Clear bit
in the Configuration register (address 00h, bit 3). Once an Interrupt event has occurred by crossing T
in the Configuration register (address 00h, bit 3). Once an Interrupt event has occurred by crossing T
hot
, then
reset, an Interrupt will occur again once the next temperature conversion has completed. The interrupts will
continue to occur in this manner until the temperature goes below T
continue to occur in this manner until the temperature goes below T
hot hyst
, at which time the Interrupt output will
automatically clear.
“One-Time Interrupt” mode operates in the following way: Exceeding T
hot
causes an Interrupt that will remain
active indefinitely until reset by reading Interrupt Status Register 1 or cleared by the INT_Clear bit in the
Configuration register. Once an Interrupt event has occurred by crossing T
Configuration register. Once an Interrupt event has occurred by crossing T
hot
, then reset, an Interrupt will not
occur again until the temperature goes below T
hot hyst
.
“Comparator” mode operates in the following way: Exceeding T
os
causes the OS output to go Low (default).
OS will remain Low until the temperature goes below T
os hyst
. Once the temperature goes below T
os hyst
, OS will
go high.
A.
This diagram does not reflect all the possible variations in the operation of the OS and INT outputs nor the OS and
Hot Temp bits. The interrupt outputs are cleared by reading the appropriate Interrupt Status Registers (addresses 01h
- 02h).
Hot Temp bits. The interrupt outputs are cleared by reading the appropriate Interrupt Status Registers (addresses 01h
- 02h).
Figure 21. Temperature Interrupt Response Diagram
Copyright © 2009–2013, Texas Instruments Incorporated
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