Texas Instruments LM96080 Evaluation Board LM96080EB/NOPB LM96080EB/NOPB Datenbogen
Produktcode
LM96080EB/NOPB
SNAS465D – SEPTEMBER 2009 – REVISED MARCH 2013
05h), the OS enable bit (bit 6), must be set high and the RST enable bit (bit 7) must be set low to enable the
OS function on the RST_OUT/OS pin. OS pin has two modes of operation: “One-Time Interrupt” and
“Comparator”. “One-Time Interrupt” mode is selected by taking bit 2 of the OS Configuration/Temperature
Resolution Register (address 06h) high. If bit 2 is taken low, “Comparator” mode is selected. Unlike the OS
pin, the OS bit in Interrupt Status Register 2 (address 02h, bit 5) functions in “Default Interrupt” and “One-
Time Interrupt” modes. The OS bit can be masked to INT pin by taking bit 5 in the Interrupt Mask Register 2
(address 04h) low. A description of “Comparator”, “Default Interrupt”, and “One-Time Interrupt” modes can be
found in
OS function on the RST_OUT/OS pin. OS pin has two modes of operation: “One-Time Interrupt” and
“Comparator”. “One-Time Interrupt” mode is selected by taking bit 2 of the OS Configuration/Temperature
Resolution Register (address 06h) high. If bit 2 is taken low, “Comparator” mode is selected. Unlike the OS
pin, the OS bit in Interrupt Status Register 2 (address 02h, bit 5) functions in “Default Interrupt” and “One-
Time Interrupt” modes. The OS bit can be masked to INT pin by taking bit 5 in the Interrupt Mask Register 2
(address 04h) low. A description of “Comparator”, “Default Interrupt”, and “One-Time Interrupt” modes can be
found in
.
Interrupt Clearing
Reading an Interrupt Status Registers (addresses 01h - 02h) will output the contents of the Register and reset
the Register. The Interrupt Status Registers clear upon being read. When the Interrupt Status Registers clear,
the INT output pin is also cleared until the Registers are updated by the monitoring loop. The INT output pin is
cleared with the INT_Clear bit (address 00h, bit 3), without affecting the contents of the Interrupt Status
Registers. When this bit is high, the LM96080 monitoring loop will stop and will resume when the bit is low.
the Register. The Interrupt Status Registers clear upon being read. When the Interrupt Status Registers clear,
the INT output pin is also cleared until the Registers are updated by the monitoring loop. The INT output pin is
cleared with the INT_Clear bit (address 00h, bit 3), without affecting the contents of the Interrupt Status
Registers. When this bit is high, the LM96080 monitoring loop will stop and will resume when the bit is low.
RST_OUT and GPO OUTPUTS
In PC applications, the open drain GPO provides a gate drive signal to an external PMOS power switch. This
external MOSFET would keep the power turned on regardless of the state of the front panel power switches
when software power control is used. In any given application, this signal is not limited to the function described
by its label. For example, since the LM96080 incorporates temperature sensing, the GPO output could also be
utilized to control power to a cooling fan. Take GPO active low by setting bit 6 in the Configuration Register
(address 00h) high.
external MOSFET would keep the power turned on regardless of the state of the front panel power switches
when software power control is used. In any given application, this signal is not limited to the function described
by its label. For example, since the LM96080 incorporates temperature sensing, the GPO output could also be
utilized to control power to a cooling fan. Take GPO active low by setting bit 6 in the Configuration Register
(address 00h) high.
RST_OUT is intended to provide a master reset to devices connected to this line. RST Enable, bit 7 of address
05h, is the RST_OUT/OS control bit that must be set high to enable this function. Setting bit 4, RESET, in the
Configuration Register (address 00h) high outputs a low pulse of at least 10 ms on this line, at the end of which
bit 4 in the Configuration Register automatically clears. Again, the label for this pin is only its suggested use. In
applications where the RST_OUT capability is not needed, it can be used for any type of digital control that
requires a 10 ms active low open drain output.
05h, is the RST_OUT/OS control bit that must be set high to enable this function. Setting bit 4, RESET, in the
Configuration Register (address 00h) high outputs a low pulse of at least 10 ms on this line, at the end of which
bit 4 in the Configuration Register automatically clears. Again, the label for this pin is only its suggested use. In
applications where the RST_OUT capability is not needed, it can be used for any type of digital control that
requires a 10 ms active low open drain output.
NAND TREE TESTS
A NAND tree is provided in the LM96080 for Automated Test Equipment (ATE) board level connectivity testing. If
the user applies a logic zero to the NTEST_IN/Reset_IN input pin, the device will be in the NAND tree test mode.
A0/NTEST_OUT will become the NAND tree output pin. To perform a NAND tree test, all pins included in the
NAND tree should be driven to 1. Beginning with IN0 and working clockwise around the chip, each pin can be
toggled and a resulting toggle can be observed on A0/NTEST_OUT. The following pins are excluded from the
NAND tree test: GNDA (analog ground), GND (digital ground), V
the user applies a logic zero to the NTEST_IN/Reset_IN input pin, the device will be in the NAND tree test mode.
A0/NTEST_OUT will become the NAND tree output pin. To perform a NAND tree test, all pins included in the
NAND tree should be driven to 1. Beginning with IN0 and working clockwise around the chip, each pin can be
toggled and a resulting toggle can be observed on A0/NTEST_OUT. The following pins are excluded from the
NAND tree test: GNDA (analog ground), GND (digital ground), V
+
(power supply), A0/NTEST_OUT,
NTEST_IN/Reset_IN and RST_OUT/OS. Allow for a typical propagation delay of 500 ns.
REGISTERS AND RAM
Address Register
The bit designations for a register are as follows:
Bit
Name
Read/Write
Description
7-0 Address Pointer
Read/Write
Address of RAM and Registers. See the tables below for detail.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Address Pointer (Power On default 00h)
A7
A6
A5
A4
A3
A2
A1
A0
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