Texas Instruments LM96080 Evaluation Board LM96080EB/NOPB LM96080EB/NOPB Datenbogen
Produktcode
LM96080EB/NOPB
IN0 Watchdog
Interrupt
Status
Registers
INT Mask
Registers
Registers
IN1 Watchdog
IN2 Watchdog
IN3 Watchdog
IN4 Watchdog
IN5 Watchdog
IN6 Watchdog
Temp Watchdog
Fan 1 Watchdog
Fan 2 Watchdog
Temp Watchdog
OS Polarity 06h[1]
OS Pin Enable 05h[6]
RST Enable 05h[7]
RESET 00h[4]
RST_OUT / OS
INT_Clear
00h[3]
00h[3]
INT
Polarity
Select 00h[2]
Polarity
Select 00h[2]
INT
Enable
00h[1]
Enable
00h[1]
INT
BTI
GPI (CI)
INT_IN
OS Status 06h[0]
SNAS465D – SEPTEMBER 2009 – REVISED MARCH 2013
THE LM96080 INTERRUPT STRUCTURE
Figure 22. Interrupt Structure
depicts the Interrupt Structure of the LM96080. Note that the number next to each input of the gate
represents a register and bit address. For example, INT_Clear 00h[3] refers to bit 3, INT_Clear, of register
address 00h. The LM96080 can generate Interrupts as a result of each of its internal WATCHDOG registers on
the analog, temperature, and fan inputs.
address 00h. The LM96080 can generate Interrupts as a result of each of its internal WATCHDOG registers on
the analog, temperature, and fan inputs.
Interrupt Inputs
External Interrupts can come from the following sources. While the label suggests a specific type or source of
Interrupt, this label is not a restriction of its usage, and it could come from any desired source:
•
Interrupt, this label is not a restriction of its usage, and it could come from any desired source:
•
BTI (Board Temperature Interrupt) -
This is an active low Interrupt intended to come from the
Overtemperature Shutdown (O.S.) output of LM75 temperature sensors. The LM75 O.S. output goes active
when its temperature exceeds a programmed threshold. Up to 8 LM75's can be connected to a single serial
bus with their O.S. output's wire or'ed to the BTI input of the LM96080. If the temperature of any LM75
exceeds its programmed limit, BTI is driven low. This generates an Interrupt via bit 1 of the Interrupt Status
Register 2 (address 02h) to notify the host of a possible overtemperature condition. To disable this feature,
set bit 1 of the Interrupt Mask Register 2 (address 04h) high. This pin also provides an internal pull-up resistor
of 10 k
when its temperature exceeds a programmed threshold. Up to 8 LM75's can be connected to a single serial
bus with their O.S. output's wire or'ed to the BTI input of the LM96080. If the temperature of any LM75
exceeds its programmed limit, BTI is driven low. This generates an Interrupt via bit 1 of the Interrupt Status
Register 2 (address 02h) to notify the host of a possible overtemperature condition. To disable this feature,
set bit 1 of the Interrupt Mask Register 2 (address 04h) high. This pin also provides an internal pull-up resistor
of 10 k
Ω
.
•
GPI (Chassis Intrusion) - This is an active high interrupt from any type of device that detects and captures
chassis intrusion violations. This could be accomplished mechanically, optically, or electrically, and circuitry
external to the LM96080 is expected to latch the event. Read this Interrupt using bit 4 of the Interrupt Status
Register 2 (address 02h), and disable it using bit 4 of the Interrupt Mask Register 2 (address 04h). The
design of the LM96080 allows this input to go high even with no power applied to the LM96080, and no
clamping or other interference with the line will occur. This line can also be pulled low for at least 10 ms by
the LM96080 to reset a typical Chassis Intrusion circuit. Accomplish this reset by setting bit 5 of Configuration
Register (address 00h) high; this bit is self-clearing.
chassis intrusion violations. This could be accomplished mechanically, optically, or electrically, and circuitry
external to the LM96080 is expected to latch the event. Read this Interrupt using bit 4 of the Interrupt Status
Register 2 (address 02h), and disable it using bit 4 of the Interrupt Mask Register 2 (address 04h). The
design of the LM96080 allows this input to go high even with no power applied to the LM96080, and no
clamping or other interference with the line will occur. This line can also be pulled low for at least 10 ms by
the LM96080 to reset a typical Chassis Intrusion circuit. Accomplish this reset by setting bit 5 of Configuration
Register (address 00h) high; this bit is self-clearing.
•
INT_IN -
This active low Interrupt provides a way to chain the INT (Interrupt) from other devices through the
LM96080 to the processor. If this pin is pulled low, then bit 7 of the Interrupt Status Register 1 (address 01h)
will go high indicating this Interrupt detection. Setting bit 1 of the Configuration Register (address 00h) will
also allow the output INT pin to go low when INT_IN goes low. To disable this feature, set bit 7 of the
Interrupt Mask Register 1 (address 03h) high.
will go high indicating this Interrupt detection. Setting bit 1 of the Configuration Register (address 00h) will
also allow the output INT pin to go low when INT_IN goes low. To disable this feature, set bit 7 of the
Interrupt Mask Register 1 (address 03h) high.
Interrupt Outputs
All Interrupts are indicated in the two Interrupt Status Registers.
•
•
INT -an output pin, not to be confused with the input INT_IN pin. This pin becomes active whenever INT_IN,
BTI, or GPI interrupts. As described in
BTI, or GPI interrupts. As described in
, INT is enabled when bit 1 of the
Configuration Register (address 00h) is set high. Bits 2 and 3 of the Configuration Register are also used to
set the polarity and state of the INT Interrupt line.
set the polarity and state of the INT Interrupt line.
•
OS -dedicated to the Temperature reading WATCHDOG. In the Fan Divisor/RST_OUT/OS Register (address
22
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: