Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE TMDSEVM6472LE Datenbogen
Produktcode
TMDSEVM6472LE
PRODUCTPREVIEW
Transmission Line
42 W
3.5 nH
Tester Pin Electronics
Z0 = 50 W
(A)
Data Sheet Timing
Reference Point
Reference Point
Output
Under
Test
Under
Test
Device Pin
(A)
4.0 pF
1.85 pF
V
ref
= 1.5 V
V
= V MIN (or V
MIN)
ref
IH
OH
V
= V MAX (or V
MAX)
ref
IL
OL
SPRS612G
–
JUNE 2009
–
REVISED JULY 2011
7
C64x+ Peripheral Information and Electrical Specifications
7.1
Parameter Information
A.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add
or
subtract
the
transmission
line
delay
(2
ns
or
longer)
from
the
data
sheet
timings.
Input requirements in this data sheet are tested with an input slew rate of
≤
4 Volts per nanosecond (V/ns) at the
device pin.
Figure 7-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
load capacitance value does not indicate the maximum load the device is capable of driving.
7.1.1
3.3-V Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.
Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V
IL
MAX and V
IH
MIN for input clocks,
V
OL
MAX and V
OH
MIN for output clocks.
Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
7.1.2
3.3-V Signal Transition Rates
All timings are tested with an input edge rate of
≤
4 Volts per nanosecond (V/ns).
7.1.3
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
good board design practice, such delays must always be taken into account. Timing values may be
118
C64x+ Peripheral Information and Electrical Specifications
Copyright
©
2009
–
2011, Texas Instruments Incorporated
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