Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE TMDSEVM6472LE Datenbogen
Produktcode
TMDSEVM6472LE
PRODUCTPREVIEW
DV
DD33
CV
CV
CV
CV
DD
DD1
DD2
DV
and other 1.8-V
supplies
DD18
V
(DDR2)
REFSSSTL
DV
DD15
and other 1.5-V
supplies
V
(RGMII)
REFHSTL
1.2-V SERDES
supplies
1
2
3
4
DV
DD33
CV
DD
All other
power supplies
1
2
SPRS612G
–
JUNE 2009
–
REVISED JULY 2011
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number
). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
7.2
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic
manner.
7.3
Power Supplies
7.3.1
Power-Supply Sequencing
TI recommends the power-supply sequence options shown in
and
. For Option 2,
after the DV
DD33
supply is stable, the remaining power supplies can be powered up at the same time as
CV
DD
as long as their supply voltage never exceeds the CV
DD
voltage until CV
DD
is stable. Note that the
word stable means voltages that have reached a valid level as described in
. Some TI
power-supply devices include an "auto-track" feature that can be used to ensure multiple supply outputs
ramp at the same time to prevent one being higher than another during startup. In all of these sequencing
requirements, the intent is to prevent a subsequent power supply voltage from exceeding a previous
power supply until the previous supply has reached a stable value.
ramp at the same time to prevent one being higher than another during startup. In all of these sequencing
requirements, the intent is to prevent a subsequent power supply voltage from exceeding a previous
power supply until the previous supply has reached a stable value.
Figure 7-4. Power-Supply Sequence (Option 1)
Figure 7-5. Power-Supply Sequence (Option 2)
Copyright
©
2009
–
2011, Texas Instruments Incorporated
C64x+ Peripheral Information and Electrical Specifications
119
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