Texas Instruments FPD- Link LVDS to FPD-Link II Embedded Clock LVDS Converter DS99R421 Evaluation Kit FPDXSDUR-43USB/NOP FPDXSDUR-43USB/NOPB Datenbogen
Produktcode
FPDXSDUR-43USB/NOPB
National Semiconductor Corporation
Date: 5/12/2008
Page 13 of 39
Page 13 of 39
DS90UR124 Rx De-serializer Board:
The USB connector J2 (mini USB) on the topside of the board provides the interface
connection for FPD-Link II signals to the Serializer board. Note: J1 (mini USB) on the
bottom side is un-stuffed and not used with the cable provided in the kit.
The SERDES de-serializer board is powered externally from the J4 (VDD) and J5 (VSS)
connectors shown below. For the de-serializer to be operational, the Power Down
(RPWDNB) and Receiver Enable (REN) switches on S1 and S2 must be set HIGH.
Rising or falling edge reference clock is also selected by S1: HIGH (rising) or LOW
(falling).
The 50 pin IDC Connector J3 provides access to the 24 bit LVCMOS and clock outputs.
connection for FPD-Link II signals to the Serializer board. Note: J1 (mini USB) on the
bottom side is un-stuffed and not used with the cable provided in the kit.
The SERDES de-serializer board is powered externally from the J4 (VDD) and J5 (VSS)
connectors shown below. For the de-serializer to be operational, the Power Down
(RPWDNB) and Receiver Enable (REN) switches on S1 and S2 must be set HIGH.
Rising or falling edge reference clock is also selected by S1: HIGH (rising) or LOW
(falling).
The 50 pin IDC Connector J3 provides access to the 24 bit LVCMOS and clock outputs.
f
J4, J5
c
FPD-Link II INPUTS
d
LVCMOS OUTPUTS
e
FUNCTION CONTROLS
f
POWER SUPPLY
d
J3
e
S1
d
JP3
Note:
Vcc and Gnd MUST be
applied externally here
Vcc and Gnd MUST be
applied externally here
c
J2
d
JP4
e
S2
c
J1 (BACKSIDE)
(UNSTUFFED)