Texas Instruments FPD- Link LVDS to FPD-Link II Embedded Clock LVDS Converter DS99R421 Evaluation Kit FPDXSDUR-43USB/NOP FPDXSDUR-43USB/NOPB Datenbogen
Produktcode
FPDXSDUR-43USB/NOPB
National Semiconductor Corporation
Date: 5/12/2008
Page 15 of 39
Page 15 of 39
Output Monitor Pins for the De-serializer Board
Table 5.
JP3: Output Lock Monitor
Reference
Description
Output = L
Output = H
JP3
LOCK Receiver
PLL LOCK
Note:
DO NOT PUT A SHORTING
JUMPER IN JP3.
DO NOT PUT A SHORTING
JUMPER IN JP3.
unlocked PLL
LOCKED
(LED2 will
illuminate)
illuminate)
JP4: PASS Monitor
Reference
Description
Output = L
Output = H
JP4
PASS
Receiver BIST monitor
PASS flag
PASS flag
Note:
DO NOT PUT A SHORTING
JUMPER IN JP1.
DO NOT PUT A SHORTING
JUMPER IN JP1.
FAIL PASS
(LED1 will
illuminate)
illuminate)