Texas Instruments AM18x eXperimenter's Kit TMDSEXP1808L TMDSEXP1808L Datenbogen
Produktcode
TMDSEXP1808L
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.11.2 DDR2/mDDR Controller Register Description(s)
DDR2/mDDR Controller Registers
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0xB000 0000
REVID
Revision ID Register
0xB000 0004
SDRSTAT
SDRAM Status Register
0xB000 0008
SDCR
SDRAM Configuration Register
0xB000 000C
SDRCR
SDRAM Refresh Control Register
0xB000 0010
SDTIMR1
SDRAM Timing Register 1
0xB000 0014
SDTIMR2
SDRAM Timing Register 2
0xB000 001C
SDCR2
SDRAM Configuration Register 2
0xB000 0020
PBBPR
Peripheral Bus Burst Priority Register
0xB000 0040
PC1
Performance Counter 1 Registers
0xB000 0044
PC2
Performance Counter 2 Register
0xB000 0048
PCC
Performance Counter Configuration Register
0xB000 004C
PCMRS
Performance Counter Master Region Select Register
0xB000 0050
PCT
Performance Counter Time Register
0xB000 00C0
IRR
Interrupt Raw Register
0xB000 00C4
IMR
Interrupt Mask Register
0xB000 00C8
IMSR
Interrupt Mask Set Register
0xB000 00CC
IMCR
Interrupt Mask Clear Register
0xB000 00E4
DRPYC1R
DDR PHY Control Register 1
0x01E2 C000
VTPIO_CTL
VTP IO Control Register
6.11.3 DDR2/mDDR Interface
This section provides the timing specification for the DDR2/mDDR interface as a PCB design and
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR
memory system without the need for a complex timing closure process. For more information regarding
guidelines for using this DDR2/mDDR specification, Understanding TI's PCB Routing Rule-Based DDR2
Timing Specification (
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR
memory system without the need for a complex timing closure process. For more information regarding
guidelines for using this DDR2/mDDR specification, Understanding TI's PCB Routing Rule-Based DDR2
Timing Specification (
6.11.3.1 DDR2/mDDR Interface Schematic
shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The
dual-memory system shown in
. Pin numbers for the device can be obtained from the pin
description section.
110
Peripheral Information and Electrical Specifications
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