Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the sample sequencer and digital comparator raw interrupt signals
are sent to the interrupt controller. Each raw interrupt signal can be masked independently.
are sent to the interrupt controller. Each raw interrupt signal can be masked independently.
Note:
For a 1 Msps rate, as the system clock frequency approaches the ADC clock frequency, it
is recommended that the application use the µDMA to store conversion data from the FIFO
to memory before processing rather than an interrupt-driven single data read. Using the
µDMA to store multiple samples before interrupting the processor amortizes interrupt
overhead across multiple transfers and prevents loss of sample data.
is recommended that the application use the µDMA to store conversion data from the FIFO
to memory before processing rather than an interrupt-driven single data read. Using the
µDMA to store multiple samples before interrupting the processor amortizes interrupt
overhead across multiple transfers and prevents loss of sample data.
Note:
Only a single
DCONSSn
bit should be set at any given time. Setting more than one of these
bits results in the
INRDC
bit from the ADCRIS register being masked, and no interrupt is
generated on any of the sample sequencer interrupt lines. It is recommended that when
interrupts are used, they are enabled on alternating samples or at the end of the sample
sequence.
interrupts are used, they are enabled on alternating samples or at the end of the sample
sequence.
ADC Interrupt Mask (ADCIM)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x008
Type RW, reset 0x0000.0000
ADC1 base: 0x4003.9000
Offset 0x008
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DCONSS0
DCONSS1
DCONSS2
DCONSS3
reserved
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MASK0
MASK1
MASK2
MASK3
reserved
DMAMASK0
DMAMASK1
DMAMASK2
DMAMASK3
reserved
RW
RW
RW
RW
RO
RO
RO
RO
RW
RW
RW
RW
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000
RO
reserved
31:20
Digital Comparator Interrupt on SS3
Description
Value
The status of the digital comparators does not affect the SS3
interrupt status.
interrupt status.
0
The raw interrupt signal from the digital comparators (
INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS3 interrupt line.
the SS3 interrupt line.
1
0
RW
DCONSS3
19
Digital Comparator Interrupt on SS2
Description
Value
The status of the digital comparators does not affect the SS2
interrupt status.
interrupt status.
0
The raw interrupt signal from the digital comparators (
INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS2 interrupt line.
the SS2 interrupt line.
1
0
RW
DCONSS2
18
December 13, 2013
1230
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)