Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 42: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for a sample executed with Sample Sequencer
3. This register is 4 bits wide and contains information for one possible sample. See the ADCSSCTL0
register on page 1259 for detailed bit descriptions.
3. This register is 4 bits wide and contains information for one possible sample. See the ADCSSCTL0
register on page 1259 for detailed bit descriptions.
Note:
When configuring a sample sequence in this register, the
END0
bit must be set.
ADC Sample Sequence Control 3 (ADCSSCTL3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0A4
Type RW, reset 0x0000.0000
ADC1 base: 0x4003.9000
Offset 0x0A4
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D0
END0
IE0
TS0
reserved
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000
RO
reserved
31:4
1st Sample Temp Sensor Select
Description
Value
The input pin specified by the ADCSSMUXn register is read
during the first sample of the sample sequence.
during the first sample of the sample sequence.
0
The temperature sensor is read during the first sample of the
sample sequence.
sample sequence.
1
0
RW
TS0
3
Sample Interrupt Enable
Description
Value
The raw interrupt is not asserted to the interrupt controller.
0
The raw interrupt signal (
INR0
bit) is asserted at the end of this
sample's conversion. If the
MASK0
bit in the ADCIM register is
set, the interrupt is promoted to the interrupt controller.
1
It is legal to have multiple samples within a sequence generate interrupts.
0
RW
IE0
2
End of Sequence
This bit must be set before initiating a single sample sequence.
Description
Value
Sampling and conversion continues.
0
This is the end of sequence.
1
0
RW
END0
1
December 13, 2013
1290
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)