Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 2: QSSI Control 1 (SSICR1), offset 0x004
The SSICR1 register contains bit fields that control various functions within the QSSI module. Master
and slave mode functionality is controlled by this register.
and slave mode functionality is controlled by this register.
QSSI Control 1 (SSICR1)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x004
Type RW, reset 0x0000.0000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x004
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LBM
SSE
MS
reserved
EOT
reserved
MODE
DIR
HSCLKEN
FSSHLDFRM
EOM
reserved
RW
RW
RW
RO
RW
RO
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0
RO
reserved
31:12
Stop Frame (End of Message)
This bit is applicable when MODE is set to Advanced, Bi- or Quad- SSI.
This bit is inserted into bit 12 of the TXFIFO data entry by the QSSI
module.
This bit is inserted into bit 12 of the TXFIFO data entry by the QSSI
module.
Description
Value
No change is transmission status.
0
End of message (Stop Frame).
1
0
RW
EOM
11
FSS Hold Frame
Description
Value
Pulse
SSInFss
at every byte (the
DSS
bit in the SSICR0 register
must be set to 0x7 (data size 8 bits) in this configuration)
0
Hold
SSInFss
for the whole frame
1
0
RW
FSSHLDFRM
10
High Speed Clock Enable
High speed clock enable is available only when operating as a master.
Description
Value
Use Input Clock
0
Use High Speed Clock
1
Note:
For proper functionality of high speed mode, the
HSCLKEN
bit in the SSICR1 register should be set before any SSI data
transfer or after applying a reset to the QSSI module. In
addition, the
transfer or after applying a reset to the QSSI module. In
addition, the
SSE
bit must be set to 0x1 before the
HSCLKEN
bit is set.
0
RW
HSCLKEN
9
1395
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller