Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
QSSI Direction of Operation
Description
Value
TX (Transmit Mode) write direction
0
RX (Receive Mode) read direction
1
0
RW
DIR
8
QSSI Mode
Description
Value
Legacy SSI mode
0x0
Bi-SSI mode
0x1
Quad-SSI Mode
0x2
Advanced SSI Mode with 8-bit packet size
0x3
0x0
RW
MODE
7:6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
5
End of Transmission
This bit is only valid for Master mode devices and operations (
MS
= 0x0).
Description
Value
The TXRIS interrupt indicates that the transmit FIFO is half full
or less.
or less.
0
The End of Transmit interrupt mode for the TXRIS interrupt is
enabled.
enabled.
1
Note:
In Freescale SPI mode only, a condition can be created where
an EOT interrupt is generated for every byte transferred even
if the FIFO is full. If the
an EOT interrupt is generated for every byte transferred even
if the FIFO is full. If the
EOT
bit has been set to 0 in an
integrated slave QSSI and the µDMA has been configured to
transfer data from this QSSI to a Master QSSI on the device
using external loopback, an EOT interrupt is generated by
the QSSI slave for every byte even if the FIFO is full.
transfer data from this QSSI to a Master QSSI on the device
using external loopback, an EOT interrupt is generated by
the QSSI slave for every byte even if the FIFO is full.
0
RW
EOT
4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
3
QSSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
the QSSI is disabled (
the QSSI is disabled (
SSE
=0).
Description
Value
The QSSI is configured as a master.
0
The QSSI is configured as a slave.
1
0
RW
MS
2
December 13, 2013
1396
Texas Instruments-Advance Information
Quad Synchronous Serial Interface (QSSI)