Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 9: QSSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
cleared. A write of 0 has no effect.
QSSI Interrupt Clear (SSIICR)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x020
Type W1C, reset 0x0000.0000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x020
Type W1C, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RORIC
RTIC
reserved
DMARXIC
DMATXIC
EOTIC
reserved
W1C
W1C
RO
RO
W1C
W1C
W1C
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
31:7
End of Transmit Interrupt Clear
Writing a 1 to this bit clears the
EOTRIS
bit in the SSIRIS register and
the
EOTMIS
bit in the SSIMIS register.
0
W1C
EOTIC
6
QSSI Transmit DMA Interrupt Clear
Writing a 1 to this bit clears the
DMATXRIS
bit in the SSIRIS register
and the
DMATXMIS
bit in the SSIMIS register.
0
W1C
DMATXIC
5
QSSI Receive DMA Interrupt Clear
Writing a 1 to this bit clears the
DMARXRIS
bit in the SSIRIS register
and the
DMARXMIS
bit in the SSIMIS register.
0
W1C
DMARXIC
4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
3:2
QSSI Receive Time-Out Interrupt Clear
Writing a 1 to this bit clears the
RTRIS
bit in the SSIRIS register and
the
RTMIS
bit in the SSIMIS register.
0
W1C
RTIC
1
QSSI Receive Overrun Interrupt Clear
Writing a 1 to this bit clears the
RORRIS
bit in the SSIRIS register and
the
RORMIS
bit in the SSIMIS register.
0
W1C
RORIC
0
December 13, 2013
1408
Texas Instruments-Advance Information
Quad Synchronous Serial Interface (QSSI)