Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen

The SSIPP register provides information regarding the properties of the QSSI module.

QSSI Peripheral Properties (SSIPP)

QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0xFC0
Type RO, reset 0x0000.000D

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

reserved

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Type

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Reset

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

HSCLK

MODE

FSSHLDFRM

reserved

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Type

1

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

Reset

Description

Reset

Type

Name

Bit/Field

Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0x0000.0000

RO

reserved

31:4

SSInFss

Hold Frame Capability

Description

Value

SSInFss

Hold Frame capability disabled.

0

SSinFss

Hold Frame capability enabled.

1

0x1

RO

FSSHLDFRM

3

Mode of Operation

Indicates what QSSI functionality is supported.

Description

Value

Legacy SSI mode

0x0

Legacy mode, Advanced SSI mode and Bi-SSI mode enabled.

0x1

Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode
enabled.

0x2

reserved

0x3

0x2

RO

MODE

2:1

High Speed Capability

Description

Value

High Speed clock capability disabled.

0

High speed clock capability enabled.

1

0x1

RO

HSCLK

0