Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
Receive FIFO Request Interrupt Mask
Description
Value
No interrupt.
0
An unmasked Receive FIFO Request interrupt was signaled
and is pending.
and is pending.
1
This bit is cleared by writing a 1 to the
RXIC
bit in the I2CSICR register.
0
RO
RXMIS
6
Transmit FIFO Request Interrupt Mask
Description
Value
No interrupt.
0
An unmasked Transmit FIFO Request interrupt was signaled
and is pending.
and is pending.
1
This bit is cleared by writing a 1 to the
TXIC
bit in the I2CSICR register.
0
RO
TXMIS
5
Transmit DMA Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked transmit DMA complete interrupt was signaled is
pending.
pending.
1
This bit is cleared by writing a 1 to the
DMATXIC
bit in the I2CSICR
register.
0
RO
DMATXMIS
4
Receive DMA Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked receive DMA complete interrupt was signaled is
pending.
pending.
1
This bit is cleared by writing a 1 to the
DMARXIC
bit in the I2CSICR
register.
0
RO
DMARXMIS
3
Stop Condition Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked STOP condition interrupt was signaled is pending.
1
This bit is cleared by writing a 1 to the
STOPIC
bit in the I2CSICR
register.
0
RO
STOPMIS
2
1491
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller