Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 24: Ethernet MAC MMC Receive Raw Interrupt Status
(EMACMMCRXRIS), offset 0x104
(EMACMMCRXRIS), offset 0x104
The MAC MMC Receive Interrupt (EMACMMCRXRIS) register maintains the interrupts that are
generated when the following happens:
generated when the following happens:
■ Receive statistic counters reach half of their maximum values (0x8000.0000 for 32-bit counter
and 0x8000 for 16-bit counter).
■ Receive statistic counters cross their maximum values (0xFFFF.FFFF for 32-bit counter and
0xFFFF for 16-bit counter).
When the Counter Stop Rollover (
CNTSTPRO
bit) in the MAC MMC Control (EMACMMCCTRL)
register is set, interrupts are set but the counter remains at all-ones. The EMACMMCRXRIS register
is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused
the interrupt is read. The least significant byte lane (bits[7:0]) of the respective counter must be read
in order to clear the interrupt bit.
is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused
the interrupt is read. The least significant byte lane (bits[7:0]) of the respective counter must be read
in order to clear the interrupt bit.
Ethernet MAC MMC Receive Raw Interrupt Status (EMACMMCRXRIS)
Base 0x400E.C000
Offset 0x104
Type RO, reset 0x0000.0000
Offset 0x104
Type RO, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
UCGF
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GBF
reserved
CRCERR
ALGNERR
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00
RO
reserved
31:18
MMC Receive Unicast Good Frame Counter Interrupt Status
Description
Value
The receive Ethernet MAC Receive Frame Count for Good
Unicast Frames (EMACRXCNTGUNI) register has not reached
half of the maximum value or the maximum value.
Unicast Frames (EMACRXCNTGUNI) register has not reached
half of the maximum value or the maximum value.
0
The receive Ethernet MAC Receive Frame Count for Good
Unicast Frames (EMACRXCNTGUNI) register has reached
half of the maximum value or the maximum value.
Unicast Frames (EMACRXCNTGUNI) register has reached
half of the maximum value or the maximum value.
1
0x0
RO
UCGF
17
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
16:7
1707
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller