Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
Full/Half Preset Level Value
Description
Value
If
CNTPRST
is set, all MMC counters get preset to almost-half
value. All octet counters get preset to 0x7FFF.F800 (
half
value - 2 KB
) and all frame-counters get preset to
0x7FFF.FFF0 (
half value - 16
).
0
If
CNTPRST
is set, all MMC counters get preset to almost-full
value. All octet counters get preset to 0xFFFF.F800 (
full
value - 2 KB
) and all frame-counters gets preset to
0xFFFF_FFF0 (
full value - 16
).
1
This bit, along with
CNTPRST
, is useful for debugging and testing the
assertion of interrupts because of MMC counter becoming half-full or
full.
full.
For 16-bit counters, the almost-half preset values are 0x7800 and
0x7FF0 for the respective octet and frame counters. Similarly, the
almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0.
0x7FF0 for the respective octet and frame counters. Similarly, the
almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0.
0
RW
CNTPRSTLVL
5
Counters Preset
Description
Value
Normal operation.
0
All counters are initialized or preset to almost full or almost half
according to the
according to the
CNTPRSTLVL
bit. The
CNTPRST
bit is cleared
automatically after 1 clock cycle.
1
This bit, along with
CNTPRSTLVL
, is useful for debugging and testing
the assertion of interrupts because of MMC counter becoming half-full
or full.
or full.
0
RW
CNTPRST
4
MMC Counter Freeze
When this bit is set, it freezes all MMC counters to their current value.
Until this bit is reset, no MMC counter is updated because of any
transmitted or received frame. If any MMC counter is read with the
Until this bit is reset, no MMC counter is updated because of any
transmitted or received frame. If any MMC counter is read with the
RSTONRD
bit set, then that counter is also cleared in this mode.
Description
Value
MMC counters are updated when a frame is transmitted or
received.
received.
0
When this bit is set, it freezes all MMC counters to their current
value. Until this bit is reset to 0, no MMC counter is updated
because of any transmitted or received frame.
value. Until this bit is reset to 0, no MMC counter is updated
because of any transmitted or received frame.
1
0
RW
CNTFREEZ
3
Reset on Read
Description
Value
No effect.
0
MMC counters are reset to zero after a read (self-clearing after
reset). The counters are cleared when the least significant byte
lane (bits[7:0]) is read.
reset). The counters are cleared when the least significant byte
lane (bits[7:0]) is read.
1
0x0
RW
RSTONRD
2
1705
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller