Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen

Description

Reset

Type

Name

Bit/Field

Received Process State

This field indicates the Receive DMA state. This field does not generate
an interrupt.

Description

Value

Stopped: Reset or stop receive command issued

0x0

Running: Fetching receive transfer descriptor

0x1

reserved

0x2

Running: Waiting for receive packet

0x3

Suspended: Receive descriptor unavailable

0x4

Running: Closing receive descriptor

0x5

Writing Timestamp

0x6

Running: Transferring the receive packet data from receive
buffer to host memory

0x7

0x0

RO

RS

19:17

Normal Interrupt Summary

Normal Interrupt Summary bit value is the logical OR of the following
when the corresponding interrupt bits are enabled in EMACDMAIM
register:

■

EMACDMARIS register, bit [0]: Transmit Interrupt

■

EMACDMARIS register, bit[2]: Transmit Buffer Unavailable

■

EMACDMARIS register, bit[6]: Receive Interrupt

■

EMACDMARIS register, bit[14]: Early Receive Interrupt

Only unmasked bits (interrupts for which interrupt enable is set in the
EMACDMAIM register) affect the Normal Interrupt Summary bit.

This is a sticky bit and must be cleared (by writing 1 to this bit) each
time a corresponding bit, which causes

NIS

to be set, is cleared.

0x0

RW1C

NIS

16