Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 57: Ethernet MAC DMA Interrupt Status (EMACDMARIS), offset 0xC14
The MAC DMA Interrupt Status (EMACDMARIS) register contains all status bits that the DMA
reports to the host. The software driver reads this register during an interrupt service routine or
polling. Most of the fields in this register cause the host to be interrupted. The bits of this register
are not cleared when read. Writing a 1 to any bit in the lower half-word of this register clears the bit
and writing a 0 has no effect. Status bits [16:0] can be masked by enabling the appropriate mask
in the MAC DMA Interrupt Mask Register (EMACDMAIM) register.
reports to the host. The software driver reads this register during an interrupt service routine or
polling. Most of the fields in this register cause the host to be interrupted. The bits of this register
are not cleared when read. Writing a 1 to any bit in the lower half-word of this register clears the bit
and writing a 0 has no effect. Status bits [16:0] can be masked by enabling the appropriate mask
in the MAC DMA Interrupt Mask Register (EMACDMAIM) register.
Ethernet MAC DMA Interrupt Status (EMACDMARIS)
Base 0x400E.C000
Offset 0xC14
Type RW, reset 0x0000.0000
Offset 0xC14
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NIS
RS
TS
AE
reserved
MMC
PMT
TT
reserved
RW1C
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TI
TPS
TU
TJT
OVF
UNF
RI
RU
RPS
RWT
ETI
reserved
FBI
ERI
AIS
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RO
RO
RW1C
RW1C
RW1C
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
31:30
Timestamp Trigger Interrupt Status
Software can read the Ethernet MAC Timestamp Status
(EMACTIMSTAT) register for the exact cause of interrupt and clear its
source to reset this bit to 0. When this bit is 1, the interrupt signal from
the MAC subsystem is high.
(EMACTIMSTAT) register for the exact cause of interrupt and clear its
source to reset this bit to 0. When this bit is 1, the interrupt signal from
the MAC subsystem is high.
Description
Value
No Timestamp interrupt has occurred.
0
An interrupt event in the Timestamp module has occurred.
1
0x0
RO
TT
29
MAC PMT Interrupt Status
Software can read the PMT Control and Status (EMACPMTCTLSTAT)
register for the exact cause of the interrupt and clear its source to reset
this bit to 0. When this bit is 1, the interrupt signal from the MAC
subsystem is high.
register for the exact cause of the interrupt and clear its source to reset
this bit to 0. When this bit is 1, the interrupt signal from the MAC
subsystem is high.
Description
Value
No PMT interrupt has occurred.
0
An interrupt event in the PMT module has occurred.
1
0x0
RO
PMT
28
1755
December 13, 2013
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Tiva
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TM4C129XNCZAD Microcontroller