Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 70: Ethernet PHY Interrupt Mask (EPHYIM), offset 0xFD4
The Ethernet PHY Interrupt Mask (EPHYIM) register is used to mask the interrupt from the Ethernet
PHY, which is either from the internal integrated PHY or an external PHY.
PHY, which is either from the internal integrated PHY or an external PHY.
Ethernet PHY Interrupt Mask (EPHYIM)
Base 0x400E.C000
Offset 0xFD4
Type RW, reset 0x0000.0000
Offset 0xFD4
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
INT
reserved
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
31:1
Ethernet PHY Interrupt Mask
Description
Value
An Ethernet PHY interrupt is suppressed and not sent to the
interrupt controller.
interrupt controller.
0
An Ethernet PHY interrupt is sent to the interrupt controller when
the
the
INT
bit is set in the EPHYRIS register.
This interrupt could be generated from either the integrated PHY
or an external PHY through the
or an external PHY through the
EN0INTR
signal depending on
the configuration chosen.
1
0
RW
INT
0
December 13, 2013
1782
Texas Instruments-Advance Information
Ethernet Controller