Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 71: Ethernet PHY Masked Interrupt Status and Clear (EPHYMISC),
offset 0xFD8
offset 0xFD8
The Ethernet Masked Interrupt Status and Clear (EPHYMISC) register displays the masked
interrupt status of the Ethernet PHY, which is either from the internal integrated PHY or an external
PHY. This register can be written to clear the EPHYRIS register.
interrupt status of the Ethernet PHY, which is either from the internal integrated PHY or an external
PHY. This register can be written to clear the EPHYRIS register.
This register is used for clearing the EPHYRIS register bits.
Ethernet PHY Masked Interrupt Status and Clear (EPHYMISC)
Base 0x400E.C000
Offset 0xFD8
Type RW1C, reset 0x0000.0000
Offset 0xFD8
Type RW1C, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
INT
reserved
RW1C
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
31:1
Ethernet PHY Status and Clear register
Reading this register provides a result which is the logical AND of the
EPHYRIS and EPHYIM registers. A write of 1 to a bit of this register
clears the corresponding bit in the EPHYRIS register.
EPHYRIS and EPHYIM registers. A write of 1 to a bit of this register
clears the corresponding bit in the EPHYRIS register.
Note:
The Ethernet MAC interrupt is an OR'd summary of both the
masked EMACRIS register output and this register. When an
Ethernet MAC interrupt is asserted, software mush check
both the EMACRIS and EMACIM registers along with this
register.
masked EMACRIS register output and this register. When an
Ethernet MAC interrupt is asserted, software mush check
both the EMACRIS and EMACIM registers along with this
register.
0
RW1C
INT
0
24.8
Ethernet PHY Register Descriptions
This section lists and describes the PHY registers, in numerical order by address. Also see “Ethernet
MAC Register Descriptions” on page 1661.
MAC Register Descriptions” on page 1661.
1783
December 13, 2013
Texas Instruments-Advance Information
Tiva
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TM4C129XNCZAD Microcontroller