Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
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Produktcode
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
Jabber Detect
This bit will not be cleared upon a read of the EPHYSTS register.
Description
Value
No Jabber.
0
Jabber condition detected. This bit has meaning only in 10 Mb/s
mode. This bit is a duplicate of the Jabber Detect bit in the
EPHYBMSR register (PHY offset 0x001).
mode. This bit is a duplicate of the Jabber Detect bit in the
EPHYBMSR register (PHY offset 0x001).
1
0
RO
JD
5
Auto-Negotiation Status
Description
Value
Auto-Negotiation not complete.
0
Auto-Negotiation complete.
1
0
RO
ANS
4
MII Loopback Status
Description
Value
Normal operation.
0
Loopback active (enabled).
1
0
RO
MIILB
3
Duplex Status
Description
Value
Half Duplex Mode
0
Full Duplex Mode
1
This bit indicates duplex status and is determined from Auto-Negotiation
or Forced Modes. Therefore, it is only valid if Auto-Negotiation is enabled
and complete and there is a valid link or if Auto-Negotiation is disabled
and there is a valid link.
or Forced Modes. Therefore, it is only valid if Auto-Negotiation is enabled
and complete and there is a valid link or if Auto-Negotiation is disabled
and there is a valid link.
0
RO
DUPLEX
2
Speed Status
Description
Value
100 Mb/s mode.
0
10 Mb/s mode.
1
This bit indicates the status of the speed and is determined from
Auto-Negotiation or Forced Modes. It is only valid if Auto-Negotiation is
enabled and complete and there is a valid link or if Auto-Negotiation is
disabled and there is a valid link.
Auto-Negotiation or Forced Modes. It is only valid if Auto-Negotiation is
enabled and complete and there is a valid link or if Auto-Negotiation is
disabled and there is a valid link.
1
RO
SPEED
1
Link Status
Description
Value
Link is not established.
0
Valid link is established (for either 10 or 100 Mb/s operation).
This bit is a duplicate of the Link Status bit in the EPHYBMSR
register (PHY offset 0x001).
This bit is a duplicate of the Link Status bit in the EPHYBMSR
register (PHY offset 0x001).
1
This bit is not cleared upon a read of the EPHYSTS register.
0
RO
LINK
0
December 13, 2013
1812
Texas Instruments-Advance Information
Ethernet Controller