Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 12: Memory Timing Parameter Register 0 for Main Flash and EEPROM
(MEMTIM0), offset 0x0C0
(MEMTIM0), offset 0x0C0
The MEMTIM0 register provides timing parameters for the main Flash and EEPROM memories.
The timing parameters apply to the memory while the system is in run or sleep mode; the clocking
for these modes is consistent and unchanged since the system clock frequency and source remains
unchanged during transitions between run-to-sleep and sleep-back-to-run. Writes to MEMTIM0 do
not have any effect on system state; the register contents are applied only when the
The timing parameters apply to the memory while the system is in run or sleep mode; the clocking
for these modes is consistent and unchanged since the system clock frequency and source remains
unchanged during transitions between run-to-sleep and sleep-back-to-run. Writes to MEMTIM0 do
not have any effect on system state; the register contents are applied only when the
MEMTIMU
bit
in the RSCLKCFG register is set. Doing so allows the software to execute out of the same memory
system for which the timing parameters are being modified.
system for which the timing parameters are being modified.
Depending on the CPU frequency, the application must program specific values into the fields of
the Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0). The following
table details the bit field values that are required for the given CPU frequency ranges.
the Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0). The following
table details the bit field values that are required for the given CPU frequency ranges.
Table 5-12. MEMTIM0 Register Configuration versus Frequency
FWS
/
EWS
FBCE
/
EBCE
FBCHT
/
EBCHT
Time Period Range (t) in ns
CPU Frequency range (f) in
MHz
0x0
1
0x0
62.5
16
0x1
0
0x2
62.5 > t ≥ 25
16 < f ≤ 40
0x2
0
0x3
25 > t ≥ 16.67
40 < f ≤60
0x3
0
0x4
16.67 > t ≥ 12.5
60< f ≤80
0x4
0
0x5
12.5 > t ≥ 10
80 < f ≤100
0x5
0
0x6
10 > t ≥ 8.33
100< f ≤120
Note:
The associated Flash and EEPROM fields in the MEMTIM0 register must be programmed
to the same values. For example, the
to the same values. For example, the
FWS
field must be programmed to the same value as
the
EWS
field.
Refer to “Flash Memory” on page 634 and “EEPROM” on page 645 for more information about Flash
and EEPROM programming.
and EEPROM programming.
Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0)
Base 0x400F.E000
Offset 0x0C0
Type RW, reset 0x0030.0030
Offset 0x0C0
Type RW, reset 0x0030.0030
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
EWS
reserved
EBCE
EBCHT
reserved
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FWS
reserved
FBCE
FBCHT
reserved
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000
RO
reserved
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December 13, 2013
288
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