Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 6: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018
This register is the raw interrupt status for the Hibernation module interrupt sources. Each bit can
be masked by clearing the corresponding bit in the HIBIM register. When a bit is masked, the
interrupt is not sent to the interrupt controller. Bits in this register are cleared by writing a 1 to the
corresponding bit in the Hibernation Interrupt Clear (HIBIC) register or by entering hibernation.
be masked by clearing the corresponding bit in the HIBIM register. When a bit is masked, the
interrupt is not sent to the interrupt controller. Bits in this register are cleared by writing a 1 to the
corresponding bit in the Hibernation Interrupt Clear (HIBIC) register or by entering hibernation.
Hibernation Raw Interrupt Status (HIBRIS)
Base 0x400F.C000
Offset 0x018
Type RO, reset 0x0000.0000
Offset 0x018
Type RO, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RTCALT0
reserved
LOWBAT
EXTW
WC
PADIOWK
RSTWK
VDDFAIL
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000
RO
reserved
31:8
VDD Fail Raw Interrupt Status
Description
Value
No VDDFAIL interrupt condition exists.
0
An interrupt is sent to the interrupt controller because of arbitrary
power removal or because one or more of the supplies (V
power removal or because one or more of the supplies (V
DD
,
V
DDA
or V
DDC
) has dropped below the defined operating range.
1
0
RO
VDDFAIL
7
Reset Pad I/O Wake-Up Raw Interrupt Status
Description
Value
The
RESET
pin has not been asserted or has not been enabled
to wake the device from hibernation.
0
An interrupt is sent to the interrupt controller because the
RESET
pin has been programmed to wake the device from hibernation.
1
0
RO
RSTWK
6
Pad I/O Wake-Up Raw Interrupt Status
Description
Value
One of the wake-enabled GPIO pins or the external
RESET
pin
has not been asserted or has not been enabled to wake the
device from hibernation.
device from hibernation.
0
An interrupt is sent to the interrupt controller because one of
the wake-enabled GPIO pins or the external
the wake-enabled GPIO pins or the external
RESET
pin has
been asserted.
1
0
RO
PADIOWK
5
December 13, 2013
594
Texas Instruments-Advance Information
Hibernation Module