Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 10: Hibernation RTC Sub Seconds (HIBRTCSS), offset 0x028
This register contains the RTC sub seconds counter and match values. The RTC value can be read
by first reading the HIBRTCC register, reading the
by first reading the HIBRTCC register, reading the
RTCSSC
field in the HIBRTCSS register, and
then rereading the HIBRTCC register. If the two values for HIBRTCC are equal, the read is valid.
Note:
Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the
WRC
bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the
WRC
bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 565. The HIBIO register and bits
RSTWK
,
PADIOWK
and
WC
of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the
CLK32EN
bit in the HIBCTL
register has been set may produce unexpected results.
Note:
There is a minimum system clock rate of three times the HIB clock rate to properly read the
HIBRTCSS register.
HIBRTCSS register.
Hibernation RTC Sub Seconds (HIBRTCSS)
Base 0x400F.C000
Offset 0x028
Type RW, reset 0x0000.0000
Offset 0x028
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RTCSSM
reserved
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RTCSSC
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
31
RTC Sub Seconds Match
The match value is contained in this field in one RTCOSC clock
increments. A read returns the current seconds match value.
increments. A read returns the current seconds match value.
0x0000
RW
RTCSSM
30:16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
15
RTC Sub Seconds Count
This field contains the sub second RTC count and is read as RTCOSC
clock units. For the 32.768-kHz clock source, this would be in units of
1/32,768 seconds.
clock units. For the 32.768-kHz clock source, this would be in units of
1/32,768 seconds.
0x0000
RO
RTCSSC
14:0
601
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller