Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
DEV_MXI
POR
RESET
SYSCLKREFCLK
(PLLC1)
SYSCLKx
CLKOUT0
Boot and
Configuration Pins
DDR2 Z Group
DDR2 Low Group
DDR2 Z/High Group
Power Supplies Stable
Hi-Z
Hi-Z
1
2
3
DDR2 High Group
DDR2 Low/High Group
Z Group
Hi-Z
Low Group
High Group
22
10
11
12
15
16
20
21
Config
9
Hi-Z
PLL1 CLOCK
DIVx CLOCK
5
6
19
7
8
14
17
18
13
23
4
SPRS605C – JULY 2009 – REVISED JUNE 2012
A.
Pin reset behavior depends on which peripheral defaults to controlling the multiplexed pin. For more details on what
pin group (e.g., Z Group, Z/Low Group, Z/High Group, etc.) each pin belongs to, see
pin group (e.g., Z Group, Z/Low Group, Z/High Group, etc.) each pin belongs to, see
, Pin Behaviors at
Reset.
Figure 7-20. Warm Reset (RESET) Timing
192
Peripheral Information and Electrical Specifications
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