Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
9
TSx_CLKO
(Positive Edge Clocking)
TSx_CTL/
TSx_DATA
(A)
TSx_CLKO
(Negative Edge Clocking)
9
7
7
6
8
8
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 7-53. Switching Characteristics Over Recommended Operating Conditions for TSIF Output
(see
) (continued)
-1G
SERIAL
PARALLEL
NO.
UNIT
OUTPUT
OUTPUT
(1)
MIN
MAX
MIN
MAX
All Others
1
7.5
1
7.5
ns
Delay time, TSx_CLKO edge to
9
t
d(TSCLKOV-TSDATAO)
TS0_WAITO,
TSx_CTL/TSx_DATA
(4)
output valid
1
16.5
1
16.5
ns
TSx_EN_WAITO
(4)
TSx_CTL/TSx_DATA output includes: TS0_ENAO, TS0_WAITO, TS0_PSTO, and TS0_DOUT[7:0] for a parallel output. For a serial
output, TSx_CTL/TSx_DATA output includes: TSx_ENAO, TSx_EN_WAITO, TSx_PSTO, and TS0_DOUT7 or TS1_DOUT.
output, TSx_CTL/TSx_DATA output includes: TSx_ENAO, TSx_EN_WAITO, TSx_PSTO, and TS0_DOUT7 or TS1_DOUT.
A.
TSx_CTL/TSx_DATA output includes: TS0_ENAO, TS0_WAITO, TS0_PSTO, and TS0_DOUT[7:0] for a parallel
output. For a serial output, TSx_CTL/TSx_DATA output includes: TSx_ENAO, TSx_EN_WAITO, TSx_PSTO, and
TS0_DOUT7 or TS1_DOUT.
output. For a serial output, TSx_CTL/TSx_DATA output includes: TSx_ENAO, TSx_EN_WAITO, TSx_PSTO, and
TS0_DOUT7 or TS1_DOUT.
Figure 7-46. TSIF Output Timing
236
Peripheral Information and Electrical Specifications
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