Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.14 Video Data Conversion Engine (VDCE)
The DM6467T Video Data Conversion Engine (VDCE) supports the following features:
•
Resize function on horizontal (HRSZ) and vertical (VRSZ) with ratio defined by 256/N (N is a natural
number that ranges from 256 to 2048) with 4 taps interpolation. Magnification ratio of horizontal resize
and vertical resize can be configured separately (different value can be configured).
number that ranges from 256 to 2048) with 4 taps interpolation. Magnification ratio of horizontal resize
and vertical resize can be configured separately (different value can be configured).
•
Anti-alias filter (combination of two kinds of low-pass filter) with horizontal 7 taps, and vertical direction.
•
Chrominance signal format conversion (CCV) on both directions, one is from 4:2:2 to 4:2:0 and one is
from 4:2:0 to 4:2:2. This function also uses 4 taps interpolation. MPEG-1 specific format (half-pixel
phased from even pixel position of luminance) is also supported.
from 4:2:0 to 4:2:2. This function also uses 4 taps interpolation. MPEG-1 specific format (half-pixel
phased from even pixel position of luminance) is also supported.
•
Edge padding for preparation of MC with unrestricted motion vector (required by MPEG-4, H.264, VC-
1). All modes (progressive, interlace frame, and interlace field) are supported (macro-block level
control that is required in H.264 is not currently supported).
1). All modes (progressive, interlace frame, and interlace field) are supported (macro-block level
control that is required in H.264 is not currently supported).
•
VC-1 range mapping in advanced profile (in case of displaying decoded reference image or trans-
coding from VC-1 to any other format of video codec).
coding from VC-1 to any other format of video codec).
•
2-bit hardware menu overlay with 256 steps of blending for each color.
7.14.1 VDCE Bus Master
The VDCE includes a bus master interface that accesses the DM646x system bus to transfer data.
shows the memory map for the VDCE interface.
Table 7-58. VDCE Master Memory Map
SIZE
START ADDRESS
END ADDRESS
VDCE ACCESS
(BYTES)
0x0000 0000
0x0FFF FFFF
256M
Reserved
0x1000 0000
0x1000 FFFF
64K
Reserved
0x1001 0000
0x1001 3FFF
16K
ARM RAM 0 (Data)
0x1001 4000
0x1001 7FFF
16K
ARM RAM 1 (Data)
0x1001 8000
0x1001 FFFF
32K
ARM ROM (Data)
0x1002 0000
0x10FF FFFF
16256K
Reserved
0x1100 0000
0x41FF FFFF
784M
0x4200 0000
0x43FF FFFF
32M
EMIFA Data (CS2)
0x4400 0000
0x45FF FFFF
32M
EMIFA Data (CS3)
0x4600 0000
0x47FF FFFF
32M
EMIFA Data (CS4)
0x4800 0000
0x49FF FFFF
32M
EMIFA Data (CS5)
0x4A00 0000
0x4BFF FFFF
32M
Reserved
0x4C00 0000
0x4FFF FFFF
64M
VLYNQ (Remote Data)
0x5000 0000
0x7FFF FFFF
768M
Reserved
0x8000 0000
0x9FFF FFFF
512M
DDR2 Memory Controller
0xA000 0000
0xBFFF FFFF
512M
Reserved
0xC000 0000
0xFFFF FFFF
1G
Reserved
240
Peripheral Information and Electrical Specifications
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