Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 4-7. CLKCTL Register Bit Descriptions (continued)
BIT
NAME
DESCRIPTION
11:8
AUD_CLK1
AUDIO_CLK1 Source.
This field selects the clock source for the AUDIO_CLK1 output.
0000 = Disabled
0001 = PLL1 AUXCLK
0010 = CRG0_VCXI
0011 = CRG1_VCXI
0100 = VP_CLKIN0
0101 = VP_CLKIN1
0110 = VP_CLKIN2
0111 = VP_CLKIN3
1000 = AUX_MXI
1001 = STC_CLKIN
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
This field selects the clock source for the AUDIO_CLK1 output.
0000 = Disabled
0001 = PLL1 AUXCLK
0010 = CRG0_VCXI
0011 = CRG1_VCXI
0100 = VP_CLKIN0
0101 = VP_CLKIN1
0110 = VP_CLKIN2
0111 = VP_CLKIN3
1000 = AUX_MXI
1001 = STC_CLKIN
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
7:4
RESERVED
Reserved. Read returns "0".
3:0
AUD_CLK0
AUDIO_CLK0 Source.
This field selects the clock source for the AUDIO_CLK0 output.
0000 = Disabled
0001 = PLL1 AUXCLK
0010 = CRG0_VCXI
0011 = CRG1_VCXI
0100 = VP_CLKIN0
0101 = VP_CLKIN1
0110 = VP_CLKIN2
0111 = VP_CLKIN3
1000 = AUX_MXI
1001 = STC_CLKIN
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
This field selects the clock source for the AUDIO_CLK0 output.
0000 = Disabled
0001 = PLL1 AUXCLK
0010 = CRG0_VCXI
0011 = CRG1_VCXI
0100 = VP_CLKIN0
0101 = VP_CLKIN1
0110 = VP_CLKIN2
0111 = VP_CLKIN3
1000 = AUX_MXI
1001 = STC_CLKIN
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
92
Device Configurations
Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s):