Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
4.4
Boot Sequence
The boot sequence is a process by which the device's memory is loaded with program and data sections,
and by which some of the device's internal registers are programmed with predetermined values. The boot
sequence is started automatically after each device-level global reset. For more details on device-level
global resets, see
and by which some of the device's internal registers are programmed with predetermined values. The boot
sequence is started automatically after each device-level global reset. For more details on device-level
global resets, see
, Reset.
There are several methods by which the memory and register initialization can take place. Each of these
methods is referred to as a boot mode. The boot mode to be used is selected at reset. For more
information on the bootmode selections, see
methods is referred to as a boot mode. The boot mode to be used is selected at reset. For more
information on the bootmode selections, see
, Boot Modes.
The device is booted through multiple means—primary bootloaders within internal ROM or EMIFA, and
secondary user bootloaders from peripherals or external memories. Boot modes, pin configurations, and
register configurations required for booting the device, are described in the following subsections.
secondary user bootloaders from peripherals or external memories. Boot modes, pin configurations, and
register configurations required for booting the device, are described in the following subsections.
4.4.1
Boot Modes
The DM6467T boot modes are determined by these device boot and configuration pins. For information
on how these pins are sampled at device reset, see
on how these pins are sampled at device reset, see
, Latching Boot and Configuration
Pins.
•
BTMODE[3:0]
•
PCIEN
•
CS2BW
•
DSPBOOT
The TMS320DM646x DMSoC ARM can boot either from asynchronous EMIF/NOR Flash or from ARM
ROM, as determined by the device boot and configuration pins at reset (BTMODE[3:0] and PCIEN). The
PCIEN pin configuration is used to select the default configuration of the EMIFA/PCI/HPI pins at reset.
This allows the DM646xT DMSoC to be PCI-compliant at reset. When PCIEN = 1, the PCI module
controls the multiplexed pins with the appropriate pullup/pulldown configuration. For all other bootmodes
(non-PCI bootmodes), the PCIEN must be cleared to "0".
ROM, as determined by the device boot and configuration pins at reset (BTMODE[3:0] and PCIEN). The
PCIEN pin configuration is used to select the default configuration of the EMIFA/PCI/HPI pins at reset.
This allows the DM646xT DMSoC to be PCI-compliant at reset. When PCIEN = 1, the PCI module
controls the multiplexed pins with the appropriate pullup/pulldown configuration. For all other bootmodes
(non-PCI bootmodes), the PCIEN must be cleared to "0".
For a more detailed description of the ROM boot modes supported by the DM646xT DMSoC, see Using
the TMS320DM646x Bootloader Application Report (literature number
the TMS320DM646x Bootloader Application Report (literature number
4.4.2
Boot Mode Registers
The DSPBOOTADDR, BOOTCMPLT, BOOTCMD, and BOOTCFG registers are used to control boot and
device configurations.
device configurations.
4.4.2.1
DSPBOOTADDR Register
The DSPBOOTADDR register contains the upper 22 bits of the DSP reset vector.
31
10
9
0
BOOTADDR[21:0]
RESERVED
R/W-0100 0010 0010 0000 0000 00
R-00 0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-6. DSPBOOTADDR Register
Table 4-8. DSPBOOTADDR Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:10
BOOTADDR[21:0]
Upper 22 bits of the C64x+ DSP boot address.
9:0
RESERVED
Reserved
Copyright © 2009–2012, Texas Instruments Incorporated
Device Configurations
93
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