Texas Instruments CC2650DK Benutzerhandbuch
Output
Signal
Time
Count
GPTMTnR=GPTMnMRGPTMTnR=GPTMnMR
0xC350
0x411A
TnPWML = 0
TnPWML = 1
TnEN set
Functional Description
When software writes the TnEN bit in the [GPT_CTL] register, the counter begins counting down until it
reaches the 0x0 state. Alternatively, if the TnWOT bit is set in the [GPT_TnMR] register, once the TnEN
bit is set, the timer waits for a trigger to begin counting. On the next counter cycle in periodic mode, the
counter reloads its start value from the [GPT_TnILR] and [GPT_TnPR] registers, and continues counting
until disabled by software clearing the TnEN bit in the [GPT_CTL] register. The timer is capable of
generating interrupts based on three types of events: rising edge, falling edge, or both. The event is
configured by the TnEVENT field of the [GPT_CTL] register, and the interrupt is enabled by setting the
TnPWMIE bit in the [GPT_TnMR] register. When the event occurs, the CnERIS bit is set in the GPTM
Raw Interrupt Status [GPT_RIS] register, and holds it until it is cleared by writing the GPTM Interrupt Clear
[GPT_ICR] register . If the capture mode event interrupt is enabled in the GPTM Interrupt Mask
[GPT_IMR] register, the GPTM also sets the CnEMIS bit in the GPTM Masked Interrupt Status [GPT_MIS]
register. Note that the interrupt status bits are not updated unless the TnPWMIE bit is set.
reaches the 0x0 state. Alternatively, if the TnWOT bit is set in the [GPT_TnMR] register, once the TnEN
bit is set, the timer waits for a trigger to begin counting. On the next counter cycle in periodic mode, the
counter reloads its start value from the [GPT_TnILR] and [GPT_TnPR] registers, and continues counting
until disabled by software clearing the TnEN bit in the [GPT_CTL] register. The timer is capable of
generating interrupts based on three types of events: rising edge, falling edge, or both. The event is
configured by the TnEVENT field of the [GPT_CTL] register, and the interrupt is enabled by setting the
TnPWMIE bit in the [GPT_TnMR] register. When the event occurs, the CnERIS bit is set in the GPTM
Raw Interrupt Status [GPT_RIS] register, and holds it until it is cleared by writing the GPTM Interrupt Clear
[GPT_ICR] register . If the capture mode event interrupt is enabled in the GPTM Interrupt Mask
[GPT_IMR] register, the GPTM also sets the CnEMIS bit in the GPTM Masked Interrupt Status [GPT_MIS]
register. Note that the interrupt status bits are not updated unless the TnPWMIE bit is set.
In this mode, the [GPT_TnR] and [GPT_TnV] registers always have the same value, as do the
[GPT_PnPS] and the [GPT_TnPV] registers.
[GPT_PnPS] and the [GPT_TnPV] registers.
The output PWM signal asserts when the counter is at the value of the [GPT_TnILR] and [GPT_TnPR]
registers (its start state), and is deasserted when the counter value equals the value in the
[GPT_TnMATCHR] and [GPT_TnPMR] registers. Software can invert the output PWM signal by setting
the TnPWML bit in the [GPT_CTL] register. Inverting the output PWM does not affect the edge detection
interrupt. Thus, if a positive-edge interrupt trigger has been set, the event-trigger interrupt will be asserted
when the PWM inversion generates a positive edge.
registers (its start state), and is deasserted when the counter value equals the value in the
[GPT_TnMATCHR] and [GPT_TnPMR] registers. Software can invert the output PWM signal by setting
the TnPWML bit in the [GPT_CTL] register. Inverting the output PWM does not affect the edge detection
interrupt. Thus, if a positive-edge interrupt trigger has been set, the event-trigger interrupt will be asserted
when the PWM inversion generates a positive edge.
shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a
50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For
this example, the start value is GPT_TnILR=0xC350 and the match value is GPT_TnMATCHR=0x411A.
this example, the start value is GPT_TnILR=0xC350 and the match value is GPT_TnMATCHR=0x411A.
Figure 13-4. 16-bit PWM Mode Example
When synchronizing the timers using the [GPT_SYNC] register, the timer must be properly configured to
avoid glitches on the CCP outputs. Both the TnPLO and the TnMRSU bits must be set in the [GPT_TnMR]
register.
avoid glitches on the CCP outputs. Both the TnPLO and the TnMRSU bits must be set in the [GPT_TnMR]
register.
shows how the CCP output operates when the TnPLO and TnMRSU bits are set and
the [GPT_TnMATCHR] register value is greater than the [GPT_TnILR] register value.
1081
SWCU117A – February 2015 – Revised March 2015
Timers
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