Texas Instruments CC2650DK Benutzerhandbuch
GPTMTnR=Y
Input Signal
Time
Count
GPTMTnR=X
GPTMTnR=Z
Z
X
Y
0xFFFF
Functional Description
Mask [GPT_IMR] register, the GPTM also sets the CnEMIS bit in the GPTM Masked Interrupt Status
[GPT_MIS] register. In this mode, the [GPT_TnR] register holds the time at which the selected input event
occurred, while the [GPT_TnV] and [GPT_TnPV] registers hold the free-running timer value and the free-
running prescaler value. These registers can be read to determine the time that elapsed between the
interrupt assertion and the entry into the ISR.
[GPT_MIS] register. In this mode, the [GPT_TnR] register holds the time at which the selected input event
occurred, while the [GPT_TnV] and [GPT_TnPV] registers hold the free-running timer value and the free-
running prescaler value. These registers can be read to determine the time that elapsed between the
interrupt assertion and the entry into the ISR.
In addition to generating interrupts a
μDMA trigger can be generated. This trigger is enabled by
configuring and enabling the appropriate
μDMA channel.
After an event has been captured, the timer does not stop counting. The timer continues to count until the
TnEN bit is cleared. When the timer reaches the timeout value, it is reloaded with 0x0 in up-count mode,
and the value from the [GPT_TnILR] and [GPT_TnPR] registers in down-count mode.
TnEN bit is cleared. When the timer reaches the timeout value, it is reloaded with 0x0 in up-count mode,
and the value from the [GPT_TnILR] and [GPT_TnPR] registers in down-count mode.
shows how input edge timing mode works. In the diagram, it is assumed that the start value of
the timer is the default value of 0xFFFF, and the timer is configured to capture rising-edge events.
Each time a rising-edge event is detected, the current count value is loaded into the [GPTIMER_TnR]
register, and is held there until another rising edge is detected (at which point the new count value is
loaded into the [GPT_TnR] register).
register, and is held there until another rising edge is detected (at which point the new count value is
loaded into the [GPT_TnR] register).
Figure 13-3. Input Edge-Time Mode Example
NOTE:
When operating in Edge-time mode, the counter uses a modulo 224 count if prescaler is
enabled, or 216 if prescaler is not enabled. If there is a possibility the edge could take longer
than the count, another timer can be used to ensure detection of the missed edge.
than the count, another timer can be used to ensure detection of the missed edge.
13.3.2.4 PWM Mode
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a 16-bit
down-counter with a start value (and thus period) defined by the [GPT_TnILR] and [GPT_TnPR] registers.
In this mode, the PWM frequency and period are synchronous events, and therefore guaranteed to be
glitch-free. PWM mode is enabled with the [GPT_TnMR] register by setting the TnAMS bit to 0x1, the
TnCM bit to 0x0, and the TnMR field to 0x1 or 0x2.
down-counter with a start value (and thus period) defined by the [GPT_TnILR] and [GPT_TnPR] registers.
In this mode, the PWM frequency and period are synchronous events, and therefore guaranteed to be
glitch-free. PWM mode is enabled with the [GPT_TnMR] register by setting the TnAMS bit to 0x1, the
TnCM bit to 0x0, and the TnMR field to 0x1 or 0x2.
shows the values that are loaded into the
timer registers when the timer is enabled.
Table 13-5. Counter Values When the Timer is Enabled in PWM Mode
Register
Count Down Mode
CountUp Mode
GPT_TnR
GPT_TnILR
Not Avaliable
GPT_TnV
GPT_TnILR
Not Avaliable
GPT_TnPV
GPT_TnPR
Not Avaliable
1080
Timers
SWCU117A – February 2015 – Revised March 2015
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