Texas Instruments CC2650DK Benutzerhandbuch
Real-Time Clock Registers
14.4.1.1 CTL Register (Offset = 0h) [reset = X]
CTL is shown in
and described in
Control This register contains various bitfields for configuration of RTC
Figure 14-2. CTL Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
COMB_EV_MASK
R-X
R/W-X
15
14
13
12
11
10
9
8
RESERVED
EV_DELAY
R-X
R/W-X
7
6
5
4
3
2
1
0
RESET
RESERVED
RTC_4KHZ_EN
RTC_UPD_EN
EN
W1C-X
R-X
R/W-X
R/W-X
R/W-X
Table 14-2. CTL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-19
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
18-16
COMB_EV_MASK
R/W
X
Eventmask selecting which delayed events that form the combined
event. Enumeration values can be combined with a logical or.
event. Enumeration values can be combined with a logical or.
0h = No event is selected for combined event.
1h = Use Channel 0 delayed event in combined event
2h = Use Channel 1 delayed event in combined event
4h = Use Channel 2 delayed event in combined event
15-12
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
11-8
EV_DELAY
R/W
X
Number of SCLK_LF clock cycles waited before generating delayed
events. (Common setting for all RTC cannels) the delayed event is
delayed
events. (Common setting for all RTC cannels) the delayed event is
delayed
0h = No delay on delayed event
1h = Delay by 1 clock cycles
2h = Delay by 2 clock cycles
3h = Delay by 4 clock cycles
4h = Delay by 8 clock cycles
5h = Delay by 16 clock cycles
6h = Delay by 32 clock cycles
7h = Delay by 48 clock cycles
8h = Delay by 64 clock cycles
9h = Delay by 80 clock cycles
Ah = Delay by 96 clock cycles
Bh = Delay by 112 clock cycles
Ch = Delay by 128 clock cycles
Dh = Delay by 144 clock cycles
7
RESET
W1C
X
RTC Counter reset. Writing 1 to this bit will reset the RTC counter.
This bit is cleared when reset takes effect
This bit is cleared when reset takes effect
6-3
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1129
SWCU117A – February 2015 – Revised March 2015
Real-Time Clock
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