Texas Instruments CC2650DK Benutzerhandbuch
Real-Time Clock Registers
14.4.1.2 EVFLAGS Register (Offset = 4h) [reset = X]
EVFLAGS is shown in
and described in
Event Flags - RTC Status This register contains event flags from the 3 RTC channels. Each flag will be
cleared when writing a '1' to the corresponding bitfield.
cleared when writing a '1' to the corresponding bitfield.
Figure 14-3. EVFLAGS Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
CH2
R-X
R/W1
C-X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
CH1
RESERVED
CH0
R-X
R/W1
R-X
R/W1
C-X
C-X
Table 14-3. EVFLAGS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-17
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
16
CH2
R/W1C
X
Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC
value matches or passes the CH2CMP value. An event will be
scheduled to occur as soon as possible when writing to CH2CMP
provided that the channel is enabled and the new value matches any
time between next RTC value and 1 second in the past Writing 1
clears this flag. Note that a new event can not occur on this channel
in first 2 SCLK_LF cycles after a clearance. AUX_SCE can read the
flag through AUX_WUC:WUEVFLAGS.AON_RTC and clear it using
AUX_WUC:WUEVCLR.AON_RTC.
value matches or passes the CH2CMP value. An event will be
scheduled to occur as soon as possible when writing to CH2CMP
provided that the channel is enabled and the new value matches any
time between next RTC value and 1 second in the past Writing 1
clears this flag. Note that a new event can not occur on this channel
in first 2 SCLK_LF cycles after a clearance. AUX_SCE can read the
flag through AUX_WUC:WUEVFLAGS.AON_RTC and clear it using
AUX_WUC:WUEVCLR.AON_RTC.
15-9
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
8
CH1
R/W1C
X
Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the
following: - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches
or passes the CH1CMP value. - CHCTL.CH1_CAPT_EN = 1 and
capture occurs. An event will be scheduled to occur as soon as
possible when writing to CH1CMP provided that the channel is
enabled, in compare mode and the new value matches any time
between next RTC value and 1 second in the past. Writing 1 clears
this flag. Note that a new event can not occur on this channel in first
2 SCLK_LF cycles after a clearance.
following: - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches
or passes the CH1CMP value. - CHCTL.CH1_CAPT_EN = 1 and
capture occurs. An event will be scheduled to occur as soon as
possible when writing to CH1CMP provided that the channel is
enabled, in compare mode and the new value matches any time
between next RTC value and 1 second in the past. Writing 1 clears
this flag. Note that a new event can not occur on this channel in first
2 SCLK_LF cycles after a clearance.
7-1
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
0
CH0
R/W1C
X
Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC
value matches or passes the CH0CMP value. An event will be
scheduled to occur as soon as possible when writing to CH0CMP
provided that the channels is enabled and the new value matches
any time between next RTC value and 1 second in the past. Writing
1 clears this flag. Note that a new event can not occur on this
channel in first 2 SCLK_LF cycles after a clearance.
value matches or passes the CH0CMP value. An event will be
scheduled to occur as soon as possible when writing to CH0CMP
provided that the channels is enabled and the new value matches
any time between next RTC value and 1 second in the past. Writing
1 clears this flag. Note that a new event can not occur on this
channel in first 2 SCLK_LF cycles after a clearance.
1131
SWCU117A – February 2015 – Revised March 2015
Real-Time Clock
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