Texas Instruments CC2650DK Benutzerhandbuch
UART_CTL
UART_MIS
UART_RIS
UART_IMSC
UART_IFLS
Clock control
Interrupt control
UART_DR
UART_IBRD
Baud rate
generator
Control / Status
PERDMACLK
Interrupt
DMA Request
DMA control
UART_DMACTL
UART_FBRD
Transmitter
Receiver
UART_LCRH
UART_CTL
UART_FR
UART_RSR/ECR
UART_ICR
Control / Status
RX FIFO
32 x 12
TX FIFO
32 x 8
Identification regiters
Control / Status
UART_PERIPHID2
UART_PERIPHID3
UART_PERIPHID1
UART_PERIPHID0
Control / Status
UART_PCELLID2
UART_PCELLID3
UART_PCELLID1
UART_PCELLID0
UARTTXD
UARTRXD
Block Diagram
19.2 Block Diagram
shows the UART module block diagram.
Figure 19-1. UART Module Block Diagram
19.3 Signal Description
lists the external signals of the UART module and describes the function of each. The UART
signals are set in the IOCFG registers. For more information on configuring GPIOs, see
, I/O
Control chapter.
Table 19-1. Signals for UART
Pin Name
Pin Number
Pin Type
(1)
Description
UARTRxD
Assigned through
I
UART module 0 receive
GPIO
UARTTxD
O
UART module 0 transmit
configuration
(1)
I = Input; O = Output; I/O = Bidirectional
19.4 Functional Description
Each CC26xx UART performs the functions of parallel-to-serial and serial-to-parallel conversions. The
CC26xx UART is similar in functionality to a 16C550 UART, but is not register-compatible.
CC26xx UART is similar in functionality to a 16C550 UART, but is not register-compatible.
The UART is configured for transmit and receive through the TXE and RXE bits of the UART Control
[UART_CTL] register. Transmit and receive are both enabled out of reset. Before any control registers are
programmed, the UART must be disabled by clearing the UARTEN bit in the [UART_CTL] register. If the
UART is disabled during a transmit or receive operation, the current transaction completes before the
UART stops.
[UART_CTL] register. Transmit and receive are both enabled out of reset. Before any control registers are
programmed, the UART must be disabled by clearing the UARTEN bit in the [UART_CTL] register. If the
UART is disabled during a transmit or receive operation, the current transaction completes before the
UART stops.
1329
SWCU117A – February 2015 – Revised March 2015
Universal Asynchronous Receivers and Transmitters (UARTS)
Copyright © 2015, Texas Instruments Incorporated