Texas Instruments CC2650DK Benutzerhandbuch
Functional Description
The start bit is valid and recognized if the UARTRXD signal is still low on the eighth cycle of the baud rate
clock otherwise the start bit is ignored. After a valid start bit is detected, successive data bits are sampled
on every sixteenth cycle of the baud rate clock. The parity bit is then checked if parity mode is enabled.
Data length and parity are defined in the [UART_LCRH] register.
clock otherwise the start bit is ignored. After a valid start bit is detected, successive data bits are sampled
on every sixteenth cycle of the baud rate clock. The parity bit is then checked if parity mode is enabled.
Data length and parity are defined in the [UART_LCRH] register.
Lastly, a valid stop-bit is confirmed if the UARTRXD signal is high, otherwise a framing error has occurred.
When a full word is received, the data is stored in the receive FIFO with any error bits associated with that
word.
When a full word is received, the data is stored in the receive FIFO with any error bits associated with that
word.
19.4.4 Modem Handshake Support
This section describes how to configure and use the modem flow control signals for UART0 when
connected as a data terminal equipment (DTE), or as a data communications equipment (DCE). A modem
is a DCE, and a computing device that connects to a modem is the DTE.
connected as a data terminal equipment (DTE), or as a data communications equipment (DCE). A modem
is a DCE, and a computing device that connects to a modem is the DTE.
19.4.4.1 Signaling
The status signals provided by UART0 differ based on whether the UART is used as a DTE or a DCE.
When used as a DTE, the modem flow control signals are defined as:
When used as a DTE, the modem flow control signals are defined as:
•
UART0CTS is Clear To Send
•
UART0RTS is Request To Send
When used as a DCE, the modem flow control signals are defined as:
•
UART0CTS is Request To Send
•
UART0RTS is Clear To Send
19.4.4.2 Flow Control
Either hardware or software can accomplish flow control. The following sections describe the different
methods.
methods.
19.4.4.2.1 Hardware Flow Control (RTS and CTS)
Hardware flow control between two devices is accomplished by connecting the UART0RTS output to the
Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the receiving
device to the UART0CTS input.
Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the receiving
device to the UART0CTS input.
The UART0CTS input controls the transmitter. The transmitter can transmit data only when the
UART0CTS input is asserted. The UART0RTS output signal indicates the state of the receive FIFO.
UART0CTS remains asserted until the preprogrammed watermark level is reached, indicating that the RX
FIFO has no space to store additional characters.
UART0CTS input is asserted. The UART0RTS output signal indicates the state of the receive FIFO.
UART0CTS remains asserted until the preprogrammed watermark level is reached, indicating that the RX
FIFO has no space to store additional characters.
The [UARTCTL] register bits CTSEN and RTSEN specify the flow control mode as shown in
.
Table 19-2. Flow Control Mode
CTSEN
RTSEN
Description
1
1
RTS and CTS flow control enabled
1
0
Only CTS flow control enabled
0
1
Only RTS flow control enabled
0
0
Both RTS and CTS flow control disabled
19.4.4.2.2 Software Flow Control (Modem Status Interrupts)
Software flow control between two devices is accomplished by using interrupts to indicate the status of the
UART. Interrupts can be generated for the U1CTS signal using bit 3 of the [UART_IMSC] register. The
raw and masked interrupt status can be checked using the [UART_RIS] and [UART_MIS] registers. These
interrupts can be cleared using the [UART_ICR] register.
UART. Interrupts can be generated for the U1CTS signal using bit 3 of the [UART_IMSC] register. The
raw and masked interrupt status can be checked using the [UART_RIS] and [UART_MIS] registers. These
interrupts can be cleared using the [UART_ICR] register.
1331
SWCU117A – February 2015 – Revised March 2015
Universal Asynchronous Receivers and Transmitters (UARTS)
Copyright © 2015, Texas Instruments Incorporated