Texas Instruments CC2650DK Benutzerhandbuch
SSIn_Clk
SSIn_Fss
SSIn_Rx
LSB
SSIn_Tx
MSB
LSB
LSB
MSB
MSB
MSB
LSB
4 to16 bits
SSIn_Clk
SSn_IFss
SSIn_Rx
Q
SSIn_Tx
MSB
MSB
LSB
LSB
4 to 16 bits
Functional Description
20.4.4.2 Motorola SPI Frame Format
The Motorola SPI interface is a 4-wire interface where the SSIn_FSS signal behaves as a slave select.
The main feature of the Motorola SPI format is that the inactive state and phase of the SSIn_CLK signal
can be programmed through the SPO and SPH bits in the [SCR0] control register.
The main feature of the Motorola SPI format is that the inactive state and phase of the SSIn_CLK signal
can be programmed through the SPO and SPH bits in the [SCR0] control register.
20.4.4.2.1 SPO Clock Polarity Bit
When the SPO clock polarity control bit is clear, the bit produces a steady-state low value on the
SSIn_CLK pin. If the SPO bit is set, the bit places a steady-state high value on the SSIn_CLK pin when
data is not being transferred.
SSIn_CLK pin. If the SPO bit is set, the bit places a steady-state high value on the SSIn_CLK pin when
data is not being transferred.
20.4.4.2.2 SPH Phase-Control Bit
The SPH phase-control bit selects the clock edge that captures data, and allows it to change state. The
state of this bit has the most impact on the first bit transmitted, by either allowing or not allowing a clock
transition before the first data capture edge. When the SPH phase-control bit is clear, data is captured on
the first clock edge transition. If the SPH bit is set, data is captured on the second clock edge transition.
state of this bit has the most impact on the first bit transmitted, by either allowing or not allowing a clock
transition before the first data capture edge. When the SPH phase-control bit is clear, data is captured on
the first clock edge transition. If the SPH bit is set, data is captured on the second clock edge transition.
20.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0
and
show single and continuous transmission signal sequences for Motorola SPI
format with SPO = 0 and SPH = 0, respectively.
Figure 20-4. Motorola SPI Format (Single Transfer) With SPO = 0 and SPH = 0
Note: Q is undefined.
Figure 20-5. Motorola SPI Format (Continuous Transfer) With SPO = 0 and SPH = 0
In this configuration, during idle periods:
•
SSIn_CLK is forced low.
•
SSIn_FSS is forced high.
•
The transmit data line SSIn_TX is arbitrarily forced low.
•
When the SSI is configured as a master, it enables the SSIn_CLK pad.
•
When the SSI is configured as a slave, it disables the SSIn_CLK pad.
If the SSI is enabled and valid data is in the TX FIFO, the SSIn_FSS master signal is driven low at the
start of transmission which causes enabling of slave data onto the SSIn_RX input line of the master. The
master SSIn_TX output pad is enabled.
start of transmission which causes enabling of slave data onto the SSIn_RX input line of the master. The
master SSIn_TX output pad is enabled.
One-half SSIn_CLK period later, valid master data is transferred to the SSIn_TX pin. Once both the
master and slave data are set, the SSIn_CLK master clock pin goes high after an additional one-half
SSIn_CLK period.
master and slave data are set, the SSIn_CLK master clock pin goes high after an additional one-half
SSIn_CLK period.
1359
SWCU117A – February 2015 – Revised March 2015
Synchronous Serial Interface (SSI)
Copyright © 2015, Texas Instruments Incorporated