Texas Instruments CC2650DK Benutzerhandbuch
SSIn_Clk
SSIn_Fss
SSIn_Tx/SSIn_Rx
MSB
LSB
LSB
MSB
4 to 16 bits
SSIn_Clk
SSIn_Fss
SSIn_Rx
SSIn_Tx
Q
MSB
MSB
LSB
LSB
4 to 16 bits
Functional Description
20.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0
and
show single and continuous transmission signal sequences, respectively, for
Motorola SPI format with SPO = 1 and SPH = 0.
Figure 20-7. Motorola SPI Frame Format (Single Transfer) With SPO = 1 and SPH = 0
Note: Q is undefined.
Figure 20-8. Motorola SPI Frame Format (Continuous Transfer) With SPO = 1 and SPH = 0
In this configuration, during idle periods:
•
SSIn_CLK is forced high.
•
SSIn_FSS is forced high.
•
The transmit data line SSIn_TX is arbitrarily forced low.
•
When the SSI is configured as a master, it enables the SSIn_CLK pad.
•
When the SSI is configured as a slave, it disables the SSIn_CLK pad.
If the SSI is enabled and valid data is in the TX FIFO, the SSIFss master signal goes low at the start of
transmission and transfers slave data onto the SSIn_RX line of the master immediately. The master
SSIn_TX output pad is enabled.
transmission and transfers slave data onto the SSIn_RX line of the master immediately. The master
SSIn_TX output pad is enabled.
One-half SSIn_CLK period later, valid master data is transferred to the SSIn_TX line. When both the
master and slave data have been set, the SSIn_CLK master clock pin becomes low after one additional
half SSIn_CLK period. Data is captured on the falling edges and propagated on the rising edges of the
SSIn_CLK signal.
master and slave data have been set, the SSIn_CLK master clock pin becomes low after one additional
half SSIn_CLK period. Data is captured on the falling edges and propagated on the rising edges of the
SSIn_CLK signal.
For a single-word transmission after all bits of the data word are transferred, the SSIn_FSS line is returned
to its IDLE high state one SSIn_CLK period after the last bit is captured.
to its IDLE high state one SSIn_CLK period after the last bit is captured.
For continuous back-to-back transmissions, the SSIn_FSS signal must pulse high between each data
word transfer as the slave-select pin freezes the data in its serial peripheral register and keeps it from
being altered if the SPH bit is clear. The master device must raise the SSIn_FSS pin of the slave device
between each data transfer to enable the serial peripheral data write. When the continuous transfer
completes, the SSIn_FSS pin returns to its IDLE state one SSIn_CLK period after the last bit is captured.
word transfer as the slave-select pin freezes the data in its serial peripheral register and keeps it from
being altered if the SPH bit is clear. The master device must raise the SSIn_FSS pin of the slave device
between each data transfer to enable the serial peripheral data write. When the continuous transfer
completes, the SSIn_FSS pin returns to its IDLE state one SSIn_CLK period after the last bit is captured.
20.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1
shows the transfer signal sequence for Motorola SPI format with SPO = 1 and SPH = 1, which
covers both single and continuous transfers.
1361
SWCU117A – February 2015 – Revised March 2015
Synchronous Serial Interface (SSI)
Copyright © 2015, Texas Instruments Incorporated