Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
Table 2-103. NVIC_ISER0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
20
SETENA20
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details).
Reading the bit returns its current enable state.
interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details).
Reading the bit returns its current enable state.
19
SETENA19
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details).
Reading the bit returns its current enable state.
interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details).
Reading the bit returns its current enable state.
18
SETENA18
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details).
Reading the bit returns its current enable state.
interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details).
Reading the bit returns its current enable state.
17
SETENA17
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details).
Reading the bit returns its current enable state.
interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details).
Reading the bit returns its current enable state.
16
SETENA16
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details).
Reading the bit returns its current enable state.
interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details).
Reading the bit returns its current enable state.
15
SETENA15
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details).
Reading the bit returns its current enable state.
interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details).
Reading the bit returns its current enable state.
14
SETENA14
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details).
Reading the bit returns its current enable state.
interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details).
Reading the bit returns its current enable state.
13
SETENA13
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details).
Reading the bit returns its current enable state.
interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details).
Reading the bit returns its current enable state.
12
SETENA12
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details).
Reading the bit returns its current enable state.
interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details).
Reading the bit returns its current enable state.
11
SETENA11
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details).
Reading the bit returns its current enable state.
interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details).
Reading the bit returns its current enable state.
10
SETENA10
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details).
Reading the bit returns its current enable state.
interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details).
Reading the bit returns its current enable state.
9
SETENA9
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details).
Reading the bit returns its current enable state.
interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details).
Reading the bit returns its current enable state.
8
SETENA8
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details).
Reading the bit returns its current enable state.
interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details).
Reading the bit returns its current enable state.
7
SETENA7
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details).
Reading the bit returns its current enable state.
interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details).
Reading the bit returns its current enable state.
6
SETENA6
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details).
Reading the bit returns its current enable state.
interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details).
Reading the bit returns its current enable state.
5
SETENA5
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details).
Reading the bit returns its current enable state.
interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details).
Reading the bit returns its current enable state.
4
SETENA4
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details).
Reading the bit returns its current enable state.
interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details).
Reading the bit returns its current enable state.
3
SETENA3
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details).
Reading the bit returns its current enable state.
interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details).
Reading the bit returns its current enable state.
138
SWCU117A – February 2015 – Revised March 2015
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