Texas Instruments CC2650DK Benutzerhandbuch
I2S Registers
22.10.1.18 STMPINTRIG Register (Offset = 48h) [reset = X]
STMPINTRIG is shown in
and described in
WCLK Counter Trigger Value for Input Pins
Figure 22-25. STMPINTRIG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
IN_START_WCNT
R-X
R/W-X
Table 22-19. STMPINTRIG Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
15-0
IN_START_WCNT
R/W
X
Compare value used to start the incoming audio streams. This bit
field shall equal the WCLK counter value during the WCLK period in
which the first input word(s) are sampled and stored to memory (i.e.
the sample at the start of the very first DMA input buffer). The value
of this register takes effect when the following conditions are met: -
One or more pins are configured as inputs in AIFDIRCFG. -
AIFDMACFG has been configured for the correct buffer size, and at
least 32 BCLK cycle ticks have happened. Note: To avoid false
triggers, this bit field should be set higher than STMPWPER.VALUE.
field shall equal the WCLK counter value during the WCLK period in
which the first input word(s) are sampled and stored to memory (i.e.
the sample at the start of the very first DMA input buffer). The value
of this register takes effect when the following conditions are met: -
One or more pins are configured as inputs in AIFDIRCFG. -
AIFDMACFG has been configured for the correct buffer size, and at
least 32 BCLK cycle ticks have happened. Note: To avoid false
triggers, this bit field should be set higher than STMPWPER.VALUE.
1441
SWCU117A – February 2015 – Revised March 2015
Integrated Interchip Sound (I2S) Module
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