Texas Instruments CC2650DK Benutzerhandbuch
I2S Registers
22.10.1.19 STMPOUTTRIG Register (Offset = 4Ch) [reset = X]
STMPOUTTRIG is shown in
and described in
.
WCLK Counter Trigger Value for Output Pins
Figure 22-26. STMPOUTTRIG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
OUT_START_WCNT
R-X
R/W-X
Table 22-20. STMPOUTTRIG Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
15-0
OUT_START_WCNT
R/W
X
Compare value used to start the outgoing audio streams. This bit
field shall equal the WCLK counter value during the WCLK period in
which the first output word(s) read from memory are clocked out (i.e.
the sample at the start of the very first DMA output buffer). The value
of this register takes effect when the following conditions are met: -
One or more pins are configured as outputs in AIFDIRCFG. -
AIFDMACFG has been configured for the correct buffer size, and 32
BCLK cycle ticks have happened. - 2 samples have been preloaded
from memory (examine the AIFOUTPTR register if necessary). Note:
The memory read access is only performed when required, i.e.
channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. Note:
To avoid false triggers, this bit field should be set higher than
STMPWPER.VALUE.
field shall equal the WCLK counter value during the WCLK period in
which the first output word(s) read from memory are clocked out (i.e.
the sample at the start of the very first DMA output buffer). The value
of this register takes effect when the following conditions are met: -
One or more pins are configured as outputs in AIFDIRCFG. -
AIFDMACFG has been configured for the correct buffer size, and 32
BCLK cycle ticks have happened. - 2 samples have been preloaded
from memory (examine the AIFOUTPTR register if necessary). Note:
The memory read access is only performed when required, i.e.
channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. Note:
To avoid false triggers, this bit field should be set higher than
STMPWPER.VALUE.
1442
Integrated Interchip Sound (I2S) Module
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated