Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
Table 2-107. NVIC_ISPR0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
SETPEND2
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details).
Reading the bit returns its current state.
interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details).
Reading the bit returns its current state.
1
SETPEND1
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details).
Reading the bit returns its current state.
interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details).
Reading the bit returns its current state.
0
SETPEND0
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details).
Reading the bit returns its current state.
interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details).
Reading the bit returns its current state.
147
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated